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參數(shù)資料
| 型號： | ORLI10G-1BM416 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封裝： | PLASTIC, BGA-416 |
| 文件頁數(shù)： | 11/76頁 |
| 文件大?。?/td> | 1222K |
| 代理商： | ORLI10G-1BM416 |
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Lattice Semiconductor
19
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
ORLI10G Demultiplexer (Rx) Detail
The demultiplexer module converts the incoming
16 bits of data at 622 MHz/850 MHz into 128 bits of
data at 78 MHz/106 MHz or 64 bits of data at 156 MHz/
212 MHz and sends it to the FPGA logic. It has been
implemented in two stages; the rst stage converts
each incoming bit into a byte stream and the second
stage bit interleaves these bytes into 128/64 bits,
depending upon the mode of operation. The low-speed
clocks are generated by this block. These clocks are
then driven back to this block from the low-speed clock
tree network. Functionally, the demultiplexer architec-
ture consists of three blocks: the serial to parallel con-
version, the counters, and the interleaving.
The rst stage of the line interface module (demulti-
plexer) converts each incoming bit of data into a byte
stream on a divided-by-8 clock. The data is rst regis-
tered on the rising edge of the clock input. The clock
dividers also runs parallel to data shift (serial to paral-
lel) on the rising edge of the input clock. An enable is
created when a complete byte is taken in. This enable
signal is used to register the serial-to-parallel con-
verted data at the high-speed input clock. This ensures
that the data can be safely transferred to the low-speed
clock. This data is then transferred to the divided clock,
allowing a timing margin of approximately half the
divided clock period.
The high-speed demultiplexer converts the incoming
data as blocks of bytes. The byte boundaries of incom-
ing data are unknown and are irrelevant to this module.
This data is then interleaved to the 128/64 bits of out-
put data, depending on the mode of operation (divide-
by-4/divide-by-8). In 10G mode, the output data is
assigned the retimed 128/64 bits of data from the rst
stage of line interface registered at the input clock [0].
In 2.5G mode, the output data is assigned four concat-
enated 32/16 bits of data from the rst stage of line
interface registered at input clocks [0 to 3]. The inter-
leaving is done at bit level because the serial-to-parallel
converter operates on bits of incoming data. In 10G
mode, it is assumed that all the incoming 16 bits of data
are synchronized to the input clock [0]. This block also
generates the clock enables used by the output line
interface (multiplexer) module for registering the data
on the high-speed clock. These enables along with the
enables from other clocks are selected through the
high-speed clock MUX for the output line interface
block.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORLI10G-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORLI10G-2BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORLI10G-3BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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