參數(shù)資料
型號(hào): ORCAORT82G5
英文描述: 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
中文描述: 1.0?.25/2.0?.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù): 33/90頁(yè)
文件大?。?/td> 1915K
代理商: ORCAORT82G5
Lucent Technologies Inc.
Lucent Technologies Inc.
33
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map
(continued)
Table 10. Memory Map Bit Descriptions
Bit/Register Name(s
)
Bit/ Register
Location (hex)
Register
Type
Default
Value
(hex)
Description
Device Register Block
(continued)
scrambler/
descrambler control
0C [6]
creg
1
0
No receive direction descramble/transmit direction
scramble.
In receive direction, descramble channel after
SONET frame recovery.
In transmit direction scramble data just before paral-
lel-to-serial conversion.
No error insertion.
Invert corresponding bit in B1 byte.
Consolidation Interrupts
0
No interrupt.
Mask interrupt in enable/mask register.
1
Interrupt.
Enable interrupt in enable/mask register.
1
transmit B1 error insert
mask [7:0]
channel A int
channel B int
channel C int
channel D int
per device int
enable/mask register
[4:0]
frame offset error flag
0F [7:0]
creg
00
0
1
10 [0]
10 [1]
10 [2]
10 [3]
10 [4]
11 [4:0]
creg
creg
creg
creg
creg
iereg
0
0
0
0
0
0
write to locked register
error flag
enable/mask register
[1:0]
12 [0]
12 [1]
13 [1:0]
iareg
iareg
iereg
0
0
0
If in the receive direction the phase offset between any
two channels exceeds 17 bytes, then a frame offset error
event will be issued. This condition is continuously moni-
tored.
If the ORT4622 core memory map has not been unlocked
(by writing A1 00 to the lock registers), and any address
other than the lockreg registers or scratch pad register is
written to, then a write to locked register event will be gen-
erated.
Channel Register Block (Channel A, Channel B, Channel C, Channel D)
Rx behavior in LOF
20, 38 50, 68 [0]
1
Receive Behavior in LOF
0
When receive direction OOF occurs, do not insert
AIS-L.
1
When receive direction OOF occurs, insert AIS-L.
Force AIS-L Control
0
Do not force AIS-L.
1
Force AIS-L.
0
Do not insert a parity error.
1
Insert parity error in parity bit of receive TOH serial
output for as long as this bit is set.
0
Set receive direction
K1/K2 bytes to 0.
1
Pass receive direction K1/K2 though pointer mover.
0
Do not insert parity error.
1
Insert parity error in the parity bit of receive direction
parallel output bus for as long as this bit is set.
Force AIS-L control
20, 38, 50, 68 [1]
0
TOH serial output port
par err ins cmd
20, 38, 50, 68 [2]
0
Rx K1/K2 source
select
parallel output bus par-
ity err ins cmd
20, 38, 50, 68 [3]
0
20, 38, 50, 68 [4]
0
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