參數(shù)資料
型號(hào)： ORCAORT82G5
英文描述： 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 32/90頁(yè)
文件大小： 1915K
代理商： ORCAORT82G5
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
32
L Lucent Technologies Inc.
Memory Map
(continued)
Table 10. Memory Map Bit Descriptions
Bit/Register
Name(s
)
Bit/
Register
Location
(hex)
Register
Type
Default
Value
(hex)
Description
Device Register Block
(continued)
Rx TOH frame and
Rx TOH clock enable
08 [4]
creg
0
0
toh_ck_fp_en = 0, can be used to 3-state rx_toh_ck_en and
rx_toh_fp signals.
Functional Mode.
TOH Output MUX Select for Port A
0
TOH output port A is multiplexed to channel B.
1
TOH output port A is multiplexed to channel A.
TOH Output MUX Select for Port C
0
TOH output port C is multiplexed to channel D.
1
TOH output port C is multiplexed to channel C.
Parallel Port Output MUX Select for Port A
0
Parallel output data bus port A is multiplexed to channel B.
1
Parallel output data bus port A is multiplexed to channel A.
Parallel Port Output MUX Select for Port C
0
Parallel output data bus port C is multiplexed to channel D.
1
Parallel output data bus port C is multiplexed to channel C.
These are the minimum and maximum thresholds values for the per
channel receive direction alignment FIFOs. If and when the minimum or
maximum threshold value is violated by a particular channel, then the
interrupt event FIFO aligner threshold error will be generated for that
channel and latched as a FIFO aligner threshold error flag in the
respective per STS-12 interrupt alarm register.
The allowable range for minimum threshold values is 0 to 23.
The allowable range for maximum threshold values is 0 to 22.
Note that the minimal and maximum FIFO aligner threshold values
apply to all four channels.
These three-per-device control signals are used in conjunction with the
per-channel A1/A2 error insert command control bits to force A1/A2
errors in the transmit direction.
If a particular channel’s A1/A2 error insert command control bit is set to
the value one, then the A1 and A2 error insert values will be inserted
into that channels respective A1 and A2 bytes. The number of consecu-
tive frames to be corrupted is determined by the number of consecutive
A1, A2 errors to generate[3:0] control bits.
The error insertion is based on a rising edge detector. As such, the con-
trol must be set to value 0 before trying to initiate a second A1/A2 cor-
ruption.
0
No loopback.
1
Receive to transmit loopback on FPGA side.
0
Even parity.
1
Odd parity.
1
serial output port A
MUX select
serial output port A
MUX select
parallel output port A
MUX select
parallel output port A
MUX select
09 [0]
09 [1]
09 [2]
09 [3]
creg
1
1
1
1
FIFO aligner thresh-
old value (min) [4:0]
FIFO aligner thresh-
old value (max) [4:0]
0A [4:0]
0B [4:0]
creg
02
15
number of consecu-
tive A1/A2 errors to
generate [3:0]
A1 error insert value
[7:0]
A2 error insert value
[7:0]
0C [3:0]
0D [7:0]
0E [7:0]
creg
00
00
00
line loopback control
0C [4]
creg
0
input/output parallel
bus parity control
0C [5]
creg
0
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