- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383723 > OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R PDF資料下載
參數(shù)資料
| 型號： | OR3TP12-6PS240I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 15/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6PS240I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Lucent Technologies Inc.
Lucent Technologies Inc.
15
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
0111
Memory Write
√
√
Fully implemented.
Target:
Writes are posted, bursting is allowed, and wait-
states generation is controllable. When the Target write
FIFO is full, the next data phase will be disconnected with-
out data (
twburstpendn
= 1), or up to eight wait-states can
be inserted (
twburstpendn
= 0). After the PCI bus transac-
tion completes and the FPGA application empties the Tar-
get write FIFO, the Target write logic is cleared.
Master:
Single and burst operations are allowed.
Target ignores, per PCI Specification Section 3.1.1.
Target ignores, per PCI Specification Section 3.1.1.
Target:
Bursting is disallowed, and no wait-states are gen-
erated. Target disconnects with data on first data word. The
FPGA portion of the device is not involved in configuration
transactions.
Master:
Single and burst operations are allowed.
Fully implemented.
Target:
Bursting is disallowed, and no wait-states are gen-
erated. Target disconnects with data on first data word. The
FPGA portion of the device is not involved in configuration
transactions.
Master:
Single and burst operations are allowed.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (4’b0110); the
user’s FPGA logic is responsible for ensuring that the Mas-
ter operation meets the special requirement that the read
request ends on a cacheline boundary.
Fully implemented. Per PCI Specification 2.1, Section
3.10.1, the PCI bus core (as a Master) automatically con-
verts a 64-bit address to a 32-bit address if the upper
32 bits are all zeros.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (0110). The user’s
FPGA logic is responsible for ensuring that the Master
operation meets the special requirement that the read
request continues to the next cacheline boundary.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory write (0111); the user’s
FPGA logic is responsible for ensuring that the Master
operation meets the special requirement that writes of com-
plete cachelines, with all byte enables, are performed.
1000
1001
1010
(reserved)
(reserved)
Configuration
Read
—
—
√
—
—
√
1011
Configuration
Write
√
√
1100
Memory Read
Multiple
√
√
1101
Dual-Access
Cycle
√
√
1110
Memory Read
Line
√
√
1111
Memory Write
and Invalidate
√
√
Command
Code
(Binary)
Command
OR3TP12
Master
Generates
OR3TP12
Target
Accepts
Description
PCI Bus Core Detailed Description
(continued)
Table 3. PCI Bus Command Descriptions
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
| OR73 | 7-input OR gate with 3x drive strength. |
| OR8GU41 | DIFFUSED TYPE (HIGH SPEED RECTIFIER APPLICATIONS) |
| ORCAORT4622 | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP127BA256-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP127BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR-401045290 | 制造商:ORTRONICS 功能描述:ORTRONICS 24 PORT MODULAR PATCH PANEL |
| OR40300011 | 制造商:ORTRONICS 功能描述:WORSTATION |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。