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參數(shù)資料
| 型號(hào)： | OR3T807PS240-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁數(shù)： | 186/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T807PS240-DB |
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Lattice Semiconductor
83
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA States of Operation
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, congura-
tion, and start-up. Figure 49 outlines these three FPGA
states.
Figure 49. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are congured based on the con-
guration mode, as determined by the mode select
inputs M[2:0]. A time-out delay is initiated when VDD
reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txxx) to allow the power supply voltage to
stabilize. The INIT and DONE outputs are low. At pow-
erup, if VDD does not rise from 2.0 V to VDD in less than
25 ms, the user should delay conguration by inputting
a low into INIT, PRGM, or RESET until VDD is greater
than the recommended minimum operating voltage
(4.75 V for OR3Cxx commercial devices and 3.0 V for
OR3Txxx devices).
At the end of initialization, the default conguration
option is that the conguration RAM is written to a low
state. This prevents shorts prior to conguration. As a
conguration option, after the rst conguration (i.e., at
reconguration), the user can recongure without
clearing the internal conguration RAM rst. The
active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
conguration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the conguration
state.
The high during conguration (HDC), low during cong-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and conguration states. HDC,
LDC
, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during conguration. For parallel master
conguration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
5-4529(F)
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
START-UP
INITIALIZATION
CONFIGURATION
RESET
OR
PRGM
LOW
PRGM
LOW
– CLEAR CONFIGURATION
– INIT LOW, HDC HIGH, LDC LOW
OPERATION
POWERUP
– POWER-ON TIME DELAY
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
YES
NO
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
WRITTEN
MEMORY
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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