參數(shù)資料
型號(hào)： OR3T807PS240-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 484 CLBS, 116000 GATES, PQFP240
封裝： PLASTIC, SQFP2-240
文件頁(yè)數(shù)： 194/203頁(yè)
文件大小： 1368K
代理商： OR3T807PS240-DB
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90
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Conguration Modes
There are eight methods for conguring the FPGA.
Seven of the conguration modes are selected on the
M0, M1, and M2 inputs. The eighth conguration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some conguration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
There are three basic FPGA conguration modes:
master, slave, and peripheral. The conguration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input.
In the three peripheral modes, the FPGA acts as a
microprocessor peripheral. Table 34 lists the functions
of the conguration mode pins. Note that two congura-
tion modes previously available on the OR2Cxx and
OR2C/TxxA devices (master parallel down and syn-
chronous peripheral) have been removed for Series 3
devices.
Table 34. Configuration Modes
*
Motorola is a registered trademark of Motorola, Inc.
Master Parallel Mode
The master parallel conguration mode is generally
used to interface to industry-standard, byte-wide mem-
ory, such as the 2764 and larger EPROMs. Figure 54
provides the connections for master parallel mode. The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads 1 byte of conguration data on the rising
edge of RCLK. The parallel bytes are internally serial-
ized starting with the least signicant bit, D0. D[7:0] of
the FPGA can be connected to D[7:0] of the micropro-
cessor only if a standard prom le format is used. If a
.bit or .rbt le is used from ispLEVER, then the user
must mirror the bytes in the .bit or .rbt le OR leave the
.bit or .rbt le unchanged and connect D[7:0] of the
FPGA to D[0:7] of the microprocessor.
Figure 54. Master Parallel Conguration Schematic
In master parallel mode, the starting memory address
is 00000 Hex, and the FPGA increments the address
for each byte loaded.
One master mode FPGA can interface to the memory
and provide conguration data on DOUT to additional
FPGAs in a daisy-chain. The conguration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
M2
M1
M0
CCLK
Configuration
Mode
Data
0
Output
Master Serial
Serial
0
1
Input
Slave Parallel
Parallel
0
1
0
Output
Microprocessor:
Motorola* Pow-
erPC
Parallel
0
1
Output
Microprocessor:
Intel i960
Parallel
1
0
Output
Master Parallel
Parallel
1
0
1
Output
Async Peripheral
Parallel
1
0
Reserved
1
Input
Slave Serial
Serial
EPROM
A[17:0]
DONE
M2
M1
M0
HDC
ORCA
SERIES
FPGA
RCLK
LDC
VDD
D[7:0]
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
VDD OR GND
PRGM
PROGRAM
A[17:0]
D[7:0]
OE
CE
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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