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| 型號(hào)： | OR3T80-4BC600I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁(yè)數(shù)： | 79/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T80-4BC600I |
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Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Lucent Technologies Inc.
17
Programmable Logic Cells (continued)
Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
is provided at configuration time, the memory acts as a
ROM (the write data and write address ports and write
port enables are not used).
Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 10 shows a
128 x 8 dual-port RAM that is implemented in eight
PLCs. This figure demonstrates data path width expan-
sion by placing two memories in parallel to achieve an
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128 x 8
RAM shown could be made to operate as a single-port
RAM by tying (bit-for-bit) the read and write addresses.
To achieve depth expansion, one or two of the write
address bits (generally the MSBs) are routed to the
write port enables as in Figure 10. For 2 bits, the bits
select which 32-word bank of RAM of the four available
from a decode of two WPE inputs is to be written. Simi-
larly, 2 bits of the read address are decoded in the
SLIC and are used to control the 3-state buffers
through which the read data passes. The write data
bus is common, with separate nibbles for width expan-
sion, across all PLCs, and the read data bus is com-
mon (again, with separate nibbles) to all PLCs at the
output of the 3-state buffers.
Figure 10 also shows a new optional capability to pro-
vide a read enable for RAMs/ROMs in Series 3 using
the SLIC cell. The read enable will 3-state the read
data bus when inactive, allowing the write data and
read data buses to be tied together if desired.
Figure 10. Memory Mode Expansion Example—128 x 8 RAM
5-5749(F)
RD[7:0]
WE
WA[6:0]
RA[6:0]
CLK
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
4
PLC
8
WD[7:0]
8
7
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
4
PLC
RD[7:4]
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
4
PLC
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
4
PLC
RD[7:4]
RE
4
PFU
SLIC
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PDF描述 |
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| OR3T80-5BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3T80-6BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3T125-4PS208I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T80-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T80-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T80-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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