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參數資料
| 型號： | OR3T80-4BC600I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁數： | 201/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T80-4BC600I |
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90
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
FPGA Configuration Modes (continued)
Asynchronous Peripheral Mode
Figure 56 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface. The microprocessor generates the
control signals to write an 8-bit byte into the FPGA. The
FPGA control inputs include active-low CS0 and active-
high CS1 chip selects and WR and RD inputs. The chip
selects can be cycled or maintained at a static level
during the configuration cycle. Each byte of data is writ-
ten into the FPGA’s D[7:0] input pins.
The FPGA provides an RDY/BUSY status output to
indicate that another byte can be loaded. A low on
RDY/BUSY indicates that the double-buffered hold/shift
registers are not ready to receive data, and this pin
must be monitored to go high before another byte of
data can be written. The shortest time RDY/BUSY is
low occurs when a byte is loaded into the hold register
and the shift register is empty, in which case the byte is
immediately transferred to the shift register. The long-
est time for RDY/BUSY to remain low occurs when a
byte is loaded into the holding register and the shift
register has just started shifting configuration data into
configuration RAM.
The RDY/BUSY status is also available on the D7 pin
by enabling the chip selects, setting WR high, and
applying RD low, where the RD input provides an output
enable for the D7 pin when RD is low. The D[6:0] pins
are not enabled to drive when RD is low and, therefore,
only act as input pins in asynchronous peripheral
mode. Optionally, the user can ignore the RDY/BUSY
status and simply wait until the maximum time it would
take for the RDY/BUSY line to go high, indicating the
FPGA is ready for more data, before writing the next
data byte.
Figure 56. Asynchronous Peripheral Configuration
Microprocessor Interface (MPI) Mode
The built-in MPI in Series 3 FPGAs is designed for use
the glueless interface for FPGA configuration and read-
back from the
PowerPC and i960 processors, respec-
tively. When enabled by the mode pins, the MPI
handles all configuration/readback control and hand-
shaking with the host processor. For single FPGA con-
figuration, the host sets the configuration control
register PRGM bit to zero then back to a one and, after
reading that the INIT signal is high in the MPI status
register, transfers data 8 bits at a time to the FPGA’s
D[7:0] input pins.
If configuring multiple FPGAs through daisy-chain
operation is desired, the MP_DAISY bit must be set in
the configuration control register of the MPI. Because
of the latency involved in a daisy-chain configuration,
the MP_HOLD_BUS bit may be set to zero rather than
one for daisy-chain operation. This allows the MPI to
acknowledge the data transfer before the configuration
information has been serialized and transferred on the
FPGA daisy-chain. The early acknowledgment frees
the host processor to perform other system tasks. Con-
figuring with the MP_HOLD_BUS bit at zero requires
that the host microprocessor poll the RDY/BUSY bit of
the MPI status register and/or use the MPI interrupt
capability to confirm the readiness of the MPI for more
configuration data.
There are two options for using the host interrupt
request in configuration mode. The configuration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more configuration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit field to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI’s readiness to receive
another byte of configuration data. A flow chart of the
MPI
configuration process is shown in Figure 59. The
MPI
status and configuration register bit maps can be
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
MICRO-
PROCESSOR
D[7:0]
CS1
M2
M1
M0
HDC
ORCA
SERIES
FPGA
8
LDC
VDD
DONE
CS0
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
BUS
CONTROLLER
ADDRESS
DECODE LOGIC
RD
WR
RDY/BUSY
INIT
PRGM
5-4484(F)
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