- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299576 > OR3T80-4BA352I FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 PDF資料下載
參數(shù)資料
| 型號： | OR3T80-4BA352I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 170/210頁 |
| 文件大小： | 2138K |
| 代理商： | OR3T80-4BA352I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁當(dāng)前第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁
62
Lucent Technologies Inc.
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
Microprocessor Interface (MPI) (continued)
PowerPC System
In Figure 43, the
ORCA FPGA is a memory-mapped
peripheral to the
PowerPC processor. The PowerPC
interface uses separate address and data buses and
has several control lines. The
ORCA chip select lines,
CS0
and CS1, are each connected to an address line
coming from the
PowerPC. In this manner, the FPGA is
capable of a transaction with the
PowerPC whenever
the address line connected to CS0 is low, the address
line for CS1 is high, and there is a valid address on
PowerPC address lines A[27:31]. Other forms of selec-
tion are possible by using the FPGA chip selects in a
different way. For example,
PowerPC address bits
A[0:26] could be decoded to select CS0 and CS1, or if
the FPGA is the only peripheral to the
PowerPC, CS0
and CS1 could be tied low and high, respectively, to
cause them to always be selected. If the MPI is not
used for FPGA configuration, decoding logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out on an output pin and then connected exter-
nally to CS0 and/or CS1. If the MPI is to be used for
configuration, any decode logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
5-5761(F)
Note: FPGA shown as a memory-mapped peripheral using CS0 and
CS1. Other decoding schemes are possible using CS0 and/or
CS1.
Figure 43.
PowerPC/MPI
The basic flow of a transaction on the
PowerPC/MPI
interface is given below. Pin descriptions are shown in
Table 16 and timing is shown in the Timing Character-
istics section of this data sheet. For both read and write
transactions, the address, chip select, and read/write
(read high, write low) signals are set up at the FPGA
pins by the
PowerPC. The PowerPC then asserts its
transfer start signal (TS) low. Data is availa ble to the
MPI
during a write at the rising clock edge after the
clock cycle during which TS is low. The transfer is
acknowledged to the
PowerPC by the low assert ion of
the TA signal. The MPI
PowerPC interface does not
support burst transfers, so the burst inhibit signal, BI, is
also asserted low during the transfer acknowledge.
The same process applies to a read from the MPI
except that the read data is expected at the FPGA data
pins by the
PowerPC at the rising edge of the clock
when TA is low. The MPI only drives TA low for one
clock cycle.
Interrupt requests can be sent to the
PowerPC asyn-
chronously to the read/write process. Interrupt requests
are sourced by the user-logic in the FPGA. The MPI will
assert the request to the
PowerPC as a direct interrupt
signal and/or a pollable bit in the MPI status register
(discussed in the MPI Setup and Control section). The
MPI
will continue to assert the interrupt request until the
user-logic deasserts its interrupt request signal.
DOUT
CCLK
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
HDC
LDC
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
BI
IRQx
TS
A26
A25
TO DAISY-
CHAINED
DEVICES
POWERPC
ORCA
8
FPGA
SERIES 3
DONE
INIT
Table 16
. PowerPC/MPI Configuration
PowerPC
Signal
ORCA Pin
Name
MPI
I/O
Function
D[0:7]
D[7:0]
I/O
8-bit data bus
A[27:31]
A[4:0]
I
5-bit
MPI address
bus
TS
RD/MPI_STRB
I
Transfer start signal
—
CS0
I
Active-low
MPI
select
—
CS1
I
Active-high
MPI
select
CLKOUT
A7/MPI_CLK
I
PowerPC interface
clock
RD/WR
A8/MPI_RW
I
Read (high)/write
(low) signal
TA
A9/MPI_ACK
O
Active-low transfer
acknowledge signal
BI
A10/MPI_BI
O
Active-low burst
transfer inhibit
signal
Any of
IRQ
[7:0]
A11/MPI_IRQ
O
Active-low interrupt
request signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T80-4BA352 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
| OR3T125-4BC432I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PBGA432 |
| OR3T80-4BC432I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA432 |
| OR3C80-4BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3C80-5BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T80-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。