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| 型號(hào)： | OR3T80-4BA352I |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 160/210頁(yè) |
| 文件大小： | 2138K |
| 代理商： | OR3T80-4BA352I |
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Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Lucent Technologies Inc.
53
Special Function Blocks (continued)
Start-Up Logic
The start-up logic block is located in the lower right cor-
ner of the FPGA. This block can be configured to coor-
dinate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using lower right corner routing resources.
These signals are described in the Start-Up subsection
of the FPGA States of Operation section.
Clock Control (CLKCNTRL) and StopCLK
There is one CLKCNTRL block in the MID section of
the interquad routing on each side of the FPGA. This
block is used to selectively distribute the Fast Clock to
the PLC array and the left (top) and right (bottom)
ExpressCLKs (ECKL and ECKR) to the side of the
array on which the CLKCNTRL block resides.
The source clock for the CLKCNTRL block comes
either from the ExpressCLK pad at the middle of the
side of the FPGA or from the corner ExpressCLK route
that comes from the corner ExpressCLK pad (at the
lower left or upper right of the device, whichever is
closer). The programmable clock manager Express-
CLK
output can also be sourced to this corner routing
for distribution at the two closest CLKCNTRL blocks.
Each CLKCNTRL block also features an invertible
StopCLK
shutoff input that is available from local rout-
ing. This feature may be used to glitchlessly stop and
start the clock at the three outputs of each CLKCNTRL
block and has the option of doing so on either the rising
or falling edge of the clock. When the clock is halted
based on its rising edge, it stops and stays at VDD.
When it is stopped based on its falling edge, it stops
and stays at GND. If the StopCLK shutoff signal meets
the CLKCNTRL setup and hold times, the clock is
stopped on the second clock cycle after the shutoff sig-
nal. A diagram of the bottom CLKCNTRL block and
StopCLK
timing is shown in Figure 35.
Notes:
CLKCNTRL output clocks are ExpressCLK left and right and Fast Clock.
Clock shutoff shown active-high acting on clock falling edge.
Figure 35. Top CLKCNTRL Function Block
CORNER ExpressCLK
CLOCK SHUTOFF
ExpressCLK RIGHT
ExpressCLK LEFT
FAST CLOCK
CLOCK SHUTOFF
OFF_SET
OFF_HLD
OFF_SET
OFF_HLD
CLKCNTRL OUTPUT
CLOCKS
5-5981(F)
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| OR3T80-4BA352 | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA352 |
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| OR3T80-4BC432I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA432 |
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| OR3C80-5BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T80-4BC432I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4BC600I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS208I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-4PS240I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T80-5BA352 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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