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參數(shù)資料
| 型號： | OR3T165-4BA352I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1024 CLBS, 120000 GATES, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 154/210頁 |
| 文件大小： | 2138K |
| 代理商： | OR3T165-4BA352I |
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Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
48
Lucent Technologies Inc.
Clock Distribution Network (continued)
Clock Distribution in the PLC Array
System Clock (SCLK)
The clock distribution network, or clock spine network,
within the PLC array is designed to minimize clock
skew while maximizing clock flexibility. Clock flexibility
is expressed in two ways: the ease with which a single
clock is routed to the entire array, and the capability to
provide multiple clocks to the PLC array.
There is one horizontal and one vertical clock spine
passing through each PLC. The horizontal clock spine
is sourced from the PIC in the same row on either the
left- or right-hand side of the array, with the source side
(left or right) alternating for each row. The vertical clock
spines are similarly sourced from the PICs alternating
from the top or bottom of a column. Each clock spine is
capable of driving one of the ten xL routing segments
that run orthogonal to it within each PLC. Full connec-
tivity to all PFUs is maintained due to the connectivity
from the xL lines to the PFU clock signals described in
the previous section; however, only an xL line in every
other row (column) needs to be driven to allow the
given clock signal to be distributed to every PFU.
Figure 32 is a high-level diagram of the Series 3 sys-
tem clock spine network with sample xL line
connections for a 4 x 4 array of PLCs.
The clock spine structure previously described pro-
vides for complete distribution of a clock from any I/O
pin to the entire PLC array by means of a single clock
spine and long lines (xL). This distribution system also
provides a means to have many different clocks routed
to many different and dispersed locations in the PLC
array. Each spine can carry a different clock signal, so
for the OR3C/T55 (which has an 18 x 18 array of PLCs,
implying nine clock spines per side), 36 input clock sig-
nals can be supported using the system clock network.
Fast Clock
Fast Clocks are high-speed, low-skew clock spines
that originate from the CLKCNTRL special function
blocks (described later). There are four Fast Clock
spines—one originating on the middle of each edge of
the array. The spines run in the interquad region of the
PLC array from their source side of the device to the
last row or column on the opposite side of the device.
The Fast Clocks connect to two long lines, xL[8] and
xL[9], that run orthogonal to the spine direction in each
PLC. These long lines can then be connected to the
PFU clock input in the same manner as the general
system clocks, and, like the system clock connections,
xL lines are only needed in every other row (column) to
distribute a clock to every PFU. The limited number of
long-line connections and the low skew of the CLKCN-
TRL source combine to make the Fast Clocks a very
robust, low-skew clock source.
Figure 32. OR3C/Txxx System Clock Distribution Overview
5-5801(F).a
(xL)
HORIZONTAL
(xL)
UNUSED
(xL)
UNUSED
SCLK SPINE
(xL)
UNUSED
SCLK SPINE
VERTICAL
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
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