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參數(shù)資料
| 型號： | OR3T125-6B432 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁數(shù)： | 155/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-6B432 |
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Lucent Technologies Inc.
49
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Clock Distribution Network (continued)
Clock Sources to the PLC Array
The source of a clock that is globally available to the
PLC array can be from any user I/O pad, any of the
ExpressCLK
pads, or an internally generated source.
System Clock
As described in the Programmable Input/Output Cells
section, PICs are grouped in adjacent pairs. Any one of
the eight pads in a PIC pair can drive a clock spine in a
row or column. For PIC pairs on the top of the chip, the
column associated with the left PIC has the clock
spine, for pairs on the bottom, the right PIC column has
the spine. The top PIC of the pair sources the spine
from the left side of the array, and the bottom PIC of the
pair sources the spine from the right side of the array.
Clock delay and skew are minimized by having a single
clock buffer per pair of PICs. The clock spine for each
pair can also be driven by one of the four PIC switching
segments (pSW) in each PIC of the pair. This allows a
signal generated in the PLC array to be routed onto the
global clock spine network. The system clock output of
the programmable clock manager (PCM) may also be
routed to the global system clock spines via the pSW
segments. Figure 33 shows the clock spine multiplex-
ing structure for a pair of PICs on the top of the array.
Fast Clock
The Fast Clock spines are sourced to the PLC array
from each side of the device by the ExpressCLK pads
via the CLKCNTRL function block (described in the
Special Function Blocks section). The ExpressCLK and
Fast Clock source from the pads is shown in Figure 34
and will be described further in the ExpressCLK Inputs
subsection.
Figure 33. PIC System Clock Spine Generation
Clocks in the PICs
Because the Series 3 FPGAs have latches and FFs in
the I/Os, it is necessary to have clock signal distribution
to the PIOs as well as in the PLC array. The system
clock, the Fast Clock, and the ExpressCLK are avail-
able for PIO clocking.
PIC System Clock
There are five local system clock lines in each PIC.
Much like the sources for a clock in the PFU, two of the
local PIC clocks are generated within the PIC from long
lines. One is generated from the set of ten PIC long
lines (pxL) that runs parallel to the PICs on a side, and
the other is generated from the set of ten long lines (xL)
from the PLC array that terminate in the PIC. Another
local PIC system clock route comes from the set of ten
xL lines in the adjacent PLC that is parallel to the side
of the array on which the PIC resides. The fourth local
PIC system clock route comes from the set of ten long
lines (xL) from the PLC array that terminate in the adja-
cent PIC that is not part of the same PIC pair. Much like
the E1 signals in the PLCs that are used to distribute a
local clock to the PFU source, the fifth local clock line in
each PIC comes from local PSW signals. This clock
signal for each PIC is shown in Figure 33. One of these
five local PIC system clocks is selected for the system
clock signal in the PIO. It is used as the PIO system
clock for both input and output clocking as selected
within the PIO. All PIOs in a PIC share the same sys-
tem clock.
PIC ExpressCLK
The ExpressCLK signal used at the PIC latches/FFs
comes from the CLKCNTRL function block that resides
in the middle of the side on which the PIC resides. The
ExpressCLK
output from the CLKCNTRL block is
divided into two signals, although the same Express-
CLK
source from the pads or the programmable clock
manager (PCM) feeds both signals. One ExpressCLK
signal goes to the PICs on the right of (above) the
CLKCNTRL block, and the other ExpressCLK signal
goes to the PICs on the left of (below) the CLKCNTRL
block on that side.
PAD A
PAD B
PAD C
PAD D
PSW[4]
PSW[5]
PSW[6]
PSW[7]
PA
D
A
PA
D
B
PA
D
C
PA
D
PS
W
[4
]
PS
W
[5
]
PS
W
[6
]
PS
W
[7
]
TO LOCAL CLOCKS
SPINE
5-5800(F)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-6BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256BA352I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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