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參數(shù)資料
| 型號： | OR3T125-6B432 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁數(shù)： | 112/210頁 |
| 文件大小： | 2138K |
| 代理商： | OR3T125-6B432 |
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Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Contents
Page
Features .......................................................................... 1
System-Level Features ................................................... 3
Description ...................................................................... 4
FPGA Overview .......................................................... 4
PLC Logic ................................................................... 4
PIC Logic .................................................................... 5
System Features ......................................................... 5
Routing ....................................................................... 5
Configuration .............................................................. 5
ORCA Foundry Development System ........................ 6
Architecture ..................................................................... 6
Programmable Logic Cells .............................................. 8
Programmable Function Unit ...................................... 8
Look-Up Table Operating Modes .............................. 10
Supplemental Logic and Interconnect
Cell (SLIC) ............................................................ 18
PLC Latches/Flip-Flops ............................................ 22
PLC Routing Resources ........................................... 24
PLC Architectural Description ................................... 31
Programmable Input/Output Cells ................................ 33
5 V Tolerant I/O ......................................................... 34
PCI Compliant I/O ..................................................... 34
Inputs ........................................................................ 35
Outputs ..................................................................... 38
PIC Routing Resources ............................................ 41
PIC Architectural Description .................................... 42
High-Level Routing Resources ..................................... 44
Interquad Routing ..................................................... 44
Programmable Corner Cell Routing .......................... 45
PIC Interquad (MID) Routing .................................... 46
Clock Distribution Network ............................................ 47
PFU Clock Sources .................................................. 47
Clock Distribution in the PLC Array .......................... 48
Clock Sources to the PLC Array ............................... 49
Clocks in the PICs .................................................... 49
ExpressCLK Inputs ................................................... 50
Selecting Clock Input Pins ........................................ 50
Special Function Blocks ................................................ 51
Single Function Blocks ............................................. 51
Boundary Scan ......................................................... 54
Microprocessor Interface (MPI) .................................... 61
PowerPC System ...................................................... 62
i960 System .............................................................. 63
MPI Interface to FPGA .............................................. 64
MPI Setup and Control ............................................. 65
Programmable Clock Manager
(PCM): (Advance Information) ....................................... 69
PCM Registers .......................................................... 70
Delay-Locked Loop (DLL) Mode ............................... 72
Phase-Locked Loop (PLL) Mode .............................. 73
PCM/FPGA Internal Interface ................................... 75
PCM Operation ......................................................... 75
PCM Detailed Programming ..................................... 76
PCM Applications ..................................................... 79
PCM Cautions ........................................................... 80
FPGA States of Operation ............................................ 81
Initialization ............................................................... 81
Configuration ............................................................ 82
Start-Up .................................................................... 83
Reconfiguration ......................................................... 84
Partial Reconfiguration .............................................. 84
Other Configuration Options ..................................... 84
Configuration Data Format ............................................ 85
Using
ORCA Foundry to Generate
Configuration RAM Data ....................................... 85
Configuration Data Frame ......................................... 85
Bit Stream Error Checking ........................................ 87
FPGA Configuration Modes .......................................... 88
Master Parallel Mode ................................................ 88
Master Serial Mode ................................................... 89
Asynchronous Peripheral Mode ................................ 90
Microprocessor Interface (MPI) Mode ....................... 90
Slave Serial Mode ..................................................... 93
Slave Parallel Mode .................................................. 93
Daisy-Chaining .......................................................... 94
Daisy-Chaining with Boundary Scan.......................... 95
Absolute Maximum Ratings .......................................... 95
Recommended Operating Conditions ........................... 95
Electrical Characteristics ............................................... 96
Timing Characteristics ................................................... 98
Description ................................................................ 98
PFU Timing ............................................................. 100
PLC Timing ............................................................. 107
SLIC Timing ............................................................ 107
PIO Timing .............................................................. 108
Special Function Blocks Timing ...............................111
Clock Timing ........................................................... 118
Configuration Timing ............................................... 125
Readback Timing .................................................... 135
Input/Output Buffer Measurement Conditions ............. 136
Output Buffer Characteristics ...................................... 137
OR3Cxx .................................................................. 137
OR3Txxx ................................................................. 138
Estimating Power Dissipation ..................................... 139
OR3Cxx .................................................................. 139
OR3Txxx ................................................................. 140
PCM Power Dissipation ........................................... 141
Pin Information ............................................................ 142
Pin Descriptions ...................................................... 142
Package Compatibility ............................................ 146
Compatibility with OR2C/TxxA Series ..................... 147
Package Thermal Characteristics ................................ 194
ΘJA .......................................................................... 194
ψ JC ......................................................................... 194
ΘJC .......................................................................... 194
ΘJB .......................................................................... 194
FPGA Maximum Junction Temperature ................... 195
Package Coplanarity .................................................... 196
Package Parasitics ...................................................... 196
Package Outline Diagrams .......................................... 197
Terms and Definitions .............................................. 197
208-Pin SQFP.......................................................... 198
208-Pin SQFP2........................................................ 199
240-Pin SQPF.......................................................... 200
240-Pin SQFP2........................................................ 201
256-Pin PBGA.......................................................... 202
352-Pin PBGA.......................................................... 203
432-Pin EBGA.......................................................... 204
600-Pin EBGA.......................................................... 205
Index ............................................................................ 206
Ordering Information ................................................... 209
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-6B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T165-4B432 | FPGA, 1024 CLBS, 120000 GATES, PBGA432 |
| OR3T165-4B600 | FPGA, 1024 CLBS, 120000 GATES, PBGA600 |
| OR3T165-4BA352I | FPGA, 1024 CLBS, 120000 GATES, PBGA352 |
| OR3T165-4BA352 | FPGA, 1024 CLBS, 120000 GATES, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-6BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1256BA352I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-6BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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