參數(shù)資料
型號： OR3L165B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 2/4頁
文件大小： 139K
代理商： OR3L165B
2
Lucent Technologies Inc.
Product Brief
November 1999
ORCA OR3LxxxB Series FPGAs
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCAOR3LxxxB include:
I
Full PCI Local Bus compliance for all devices in
3.3 V and 5 V PCI systems. Pin-selectable I/O
clamping diodes provide 3.3 V and 5 V compliance
and 5 V tolerance.
I
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC
processors with user-configurable
address space provided.
I
Parallel readback of configuration data capability with
the built-in microprocessor interface.
I
Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
I
True internal 3-state, bidirectional buses with simple
control provided by the SLIC.
I
32 x 4 RAM per PFU, configurable as single- or dual-
port. Create large, fast RAM/ROM blocks (128 x 8 in
only eight PFUs) using the SLIC decoders as bank
drivers.
I
Full UTOPIA Level III I/O compliance (5.0 ns
CLK -> OUT, 2.0 ns setup with 0 ns hold).
* i960is a registered trademark of Intel Corporation.
PowerPCis a registered trademark of International Business
Machines, Inc.
Table 2. ORCA Series 3L System Performance
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain
only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Parameter
# PFUs
2
2
-7
151
151
-8
176
176
Unit
MHz
MHz
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
36-bit Parity Check (internal)
11.5
8
15
38
93
129
46
116
152
MHz
MHz
MHz
4
4
173
231
209
277
MHz
MHz
8
8
151
151
181
181
MHz
MHz
0.25
0
2.30
1.29
2.00
1.12
ns
ns
2
0
2
7.97
3.75
7.97
6.84
3.16
6.84
ns
ns
ns
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相關代理商/技術參數(shù)
參數(shù)描述
OR3L165B7BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 8192 LUT 516 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L165B7BA352I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 8192 LUT 516 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L165B7BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 8192 LUT 516 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L165B7BC432I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 8192 LUT 516 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L165B7BM680-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 8192 LUT 516 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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