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參數(shù)資料
| 型號： | OR3C804PS208-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁數(shù)： | 4/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804PS208-DB |
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Lattice Semiconductor
101
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics
Description
To dene speed grades, the
ORCA Series part number
designation (see Ordering Information) uses a single-
digit number to designate a speed grade. This number
is not related to any single ac parameter. Higher num-
bers indicate a faster set of timing parameters. The
actual speed sorting is based on testing the delay in a
path consisting of an input buffer, combinatorial delay
through all PLCs in a row, and an output buffer. Other
tests are then done to verify other delay parameters,
such as routing delays, setup times to FFs, etc.
The most accurate timing characteristics are reported
by the timing analyzer in the ispLEVER Development
System. A timing report provided by the development
system after layout divides path delays into logic and
routing delays. The timing analyzer can also provide
logic delays prior to layout. While this allows routing
budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing given in
Table 41—Table 48, symbol names are generally a
concatenation of the PFU operating mode (as dened
in Table 3) and the parameter type. The setup, hold,
and propagation delay parameters, dened below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
The values given for the parameters are the same as
those used during production testing and speed bin-
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-
ture and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (
ΘJA), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
TJmax = TAmax + (P
ΘJA) °C
Note
: The user must determine this junction tempera-
ture to see if the delays from ispLEVER should
be derated based on the following derating
tables.
ply and junction temperature derating for OR3Cxx com-
mercial and industrial devices. Table 40 provides the
same information for the OR3Txxx devices (both com-
mercial and industrial). The delay values in this data
sheet and reported by ispLEVER are shown as 1.00 in
the tables. The method for determining the maximum
junction temperature is dened in the Package Thermal
Characteristics section. Taken cumulatively, the range
of parameter values for best-case vs. worst-case pro-
cessing, supply voltage, and junction temperature can
approach 3 to 1.
Table 38. Derating for Commercial Devices
(OR3Cxx)
Table 39. Derating for Industrial Devices (OR3Cxx)
Table 40. Derating for Commercial/Industrial
Devices (OR3Txxx)
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
TJ
(C)
Power Supply Voltage
4.75 V
5.0 V
5.25 V
0
0.81
0.79
0.77
25
0.85
0.83
0.81
85
1.00
0.97
0.95
100
1.05
1.02
1.00
125
1.12
1.09
1.07
TJ
(C)
Power Supply Voltage
4.5 V
4.75 V
5.0 V
5.25 V
5.5 V
—40
0.71
0.70
0.68
0.66
0.65
0
0.80
0.78
0.76
0.74
0.73
25
0.84
0.82
0.80
0.78
0.77
85
1.00
0.97
0.94
0.93
0.91
100
1.05
1.01
0.99
0.97
0.95
125
1.12
1.09
1.06
1.04
1.02
TJ
(C)
Power Supply Voltage
3.0 V
3.3 V
3.6 V
—40
0.73
0.66
0.61
0
0.82
0.73
0.68
25
0.87
0.78
0.72
85
1.00
0.90
0.83
100
1.04
0.94
0.87
125
1.10
1.00
0.92
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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|---|---|
| OR3T1256PS208I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T306S240I-DB | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4PS208I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS240I-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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