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| 型號(hào)： | OR3C804PS208-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁(yè)數(shù)： | 101/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804PS208-DB |
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Lattice Semiconductor
19
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Supplemental Logic and Interconnect Cell
(SLIC)
Each PLC contains a supplemental logic and intercon-
nect cell (SLIC) embedded within the PLC routing, out-
side of the PFU. As its name indicates, the SLIC
performs both logic and interconnect (routing) func-
tions. Its main features are 3-statable, bidirectional
buffers, and a
PAL-like decoder capability. Figure 11
shows a diagram of a SLIC with all of its features
shown. All modes of the SLIC are not available at one
time.
Each SLIC contains ten bidirectional (BIDI) buffers,
each buffer capable of driving left and/or right out of the
SLIC. These BIDI buffers are twin-quad in nature and
are segregated into two groups of four (nibbles) and a
third group of two for control. Each of these groups of
BIDIs can drive from the left (BLI[9:0]) to the right
(BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0]), or
from the central input (I[9:0]) to the left and/or right.
This central input comes directly from the PFU outputs
(O[9:0]). Each of the BIDIs in the nibble-wide groups
also has a 3-state buffer capability, but not the third
group.
There is one 3-state control (TRI) for each SLIC, with
the capability to invert or disable the 3-state control for
each group of four BIDIs. Separate 3-state control for
each nibble-wide group is achievable by using the
SLIC’s decoder (DEC) output, driven by the group of
two BIDIs, to control the 3-state of one BIDI nibble
while using the TRI signal to control the 3-state of the
other BIDI nibble. Figure 12 and Figure 13 show the
SLIC in buffer mode with available 3-state control from
the TRI and DEC signals. If the entire SLIC is acting in
a buffer capacity, the DEC output may be used to gen-
erate a constant logic 1 (VHI) or logic 0 (VLO) signal for
general use.
The SLIC may also be used to generate
PAL-like AND-
OR with optional INVERT (AOI) functions or a decoder
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and 2-
input AND for the other two buffers). These AND gates
then feed into a 3-input gate that can be congured as
either an AND gate or an OR gate. The output of the 3-
input gate is invertible and is output at the DEC output
of the SLIC. Figure 16 shows the SLIC in full decoder
mode.
The functionality of the SLIC is parsed by the two
nibble-wide groups and the 2-bit buffer group. Each of
these groups may operate independently as BIDI buff-
ers (with or without 3-state capability for the nibble-
wide groups) or as a
PAL/decoder.
As discussed in the memory mode section, if the SLIC
is placed into one of the modes where it contains both
buffers and a decode or AOI function (e.g.,
BUF_BUF_DEC mode), the DEC output can be gated
with the 3-state input signal. This allows up to a 6-input
decode (e.g., BUF_DEC_DEC mode) plus the 3-state
input to control the enable/disable of up to four buffers
per SLIC. Figure 12—Figure 16 show several congu-
rations of the SLIC, while Table 6 shows all of the pos-
sible modes.
Table 6. SLIC Modes
Mode
#
Mode
BUF
[3:0]
BUF
[7:4]
BUF
[9:8]
1
BUFFER
Buffer
2
BUF_BUF_DEC
Buffer
Decoder
3
BUF_DEC_BUF
Buffer
Decoder
Buffer
4
BUF_DEC_DEC
Buffer
Decoder Decoder
5
DEC_BUF_BUF
Decoder
Buffer
6
DEC_BUF_DEC Decoder
Buffer
Decoder
7
DEC_DEC_BUF Decoder Decoder
Buffer
8
DECODER
Decoder Decoder Decoder
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T1256PS208I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T306S240I-DB | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4PS208I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS240I-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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