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| 型號(hào)： | OR3C804PS208-DB |
| 廠(chǎng)商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 116000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁(yè)數(shù)： | 24/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3C804PS208-DB |
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12
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Table 4. Control Input Functionality
Mode
CLK
LSR
CE
ASWE
SEL
Logic
CLK to all latches/
FFs
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Select between LUT
input and direct input
for eight latches/FFs
Half Logic/
Half Ripple
CLK to all latches/
FFs
LSR to all latches/FF,
enabled per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Select between LUT
input and direct input
for eight latches/FFs
Ripple
CLK to all latches/
FFs
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Select between LUT
input and direct input
for eight latches/FFs
Memory
(RAM)
CLK to RAM
Port enable 2
Port enable 1
Write enable
Not used
Memory
(ROM)
Optional for sync.
outputs
Not used
Logic Mode
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in exible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and softwired LUT (SWL) mode. Combinations of these
submodes are possible in each PFU.
F4 mode, shown simplied in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K0 and K1, K2
and K3, K4 and K5, K6 and K7) can be multiplexed, and
the output always goes to the even-numbered output of
the pair.
The F5 submode of the LUT operation, shown simpli-
ed in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the fth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
5-5970(F)
Figure 4. Simplied F4 and F5 Logic Modes
K7
F7
K7
F6
K6
F5D
K6
F6
K5
F5
K5
F4
K4
F5C
K4
F4
K3
F3
K3
F2
K2
F5B
K2
F2
K1
F1
K1
F0
K0
F5A
K0
F0
K7/K6
F6
K5/K4
F4
K3/K2
F2
K1/K0
F0
F5 MODE
MULTIPLEXED F4 MODE
F4 MODE
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T1256PS208I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T1256PS240-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1256PS240I-DB | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| OR3T1257PS208-DB | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| OR3T306S240I-DB | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-4PS208I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-4PS240 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-4PS240I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C804PS240I-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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