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| 型號(hào)： | OR3C80-5B432 |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁(yè)數(shù)： | 50/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3C80-5B432 |
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Lucent Technologies Inc.
143
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Pin Information (continued)
Table 68. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
M3
I
I/O
During powerup and initialization, M3 is used to select the speed of the internal oscillator dur-
ing configuration with their values latched on the rising edge of INIT. When M3 is low, the
oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configura-
tion, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
TDI, TCK,
TMS
I
I/O
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once con-
figuration is complete. Even if boundary scan is not used, either TCK or TMS must be held at
logic 1 during configuration. Each pin has a pull-up enabled during configuration.
After configuration, these pins are user-programmable I/O (see Note).
RDY/RCLK/
MPI_ALE
O
I
I/O
During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
In
i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
HDC
O
I/O
High During Configuration is output high until configuration is complete. It is used as a control
output, indicating that configuration is not complete.
After configuration, this pin is a user-programmable I/O pin (see Note).
LDC
O
I/O
Low During Configuration
is output low until configuration is complete. It is used as a control out-
put, indicating that configuration is not complete.
After configuration, this pin is a user-programmable I/O pin (see Note).
INIT
I/O
INIT
is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain out-
put, INIT is held low during power stabilization and internal clearing of memory. As an active-
low input, INIT holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
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| OR3T125-4B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-4BA352I | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C805BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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