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參數資料
| 型號： | OR2T04A-3S160I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現場可編程門陣列 |
| 文件頁數： | 35/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-3S160I |
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Lucent Technologies Inc.
35
Data Sheet
June 1999
ORCA Series 2 FPGAs
Interquad Routing
(continued)
5-4201(F).r4
Figure 31. Horizontal Subquad Routing
Connectivity
The X4 and XH lines make the only connections to the
subquad lines; therefore, the array remains symmetri-
cal and homogeneous. Since each subquad is made
from a 4 x 4 array of PLCs, the distance between sets
of subquad lines is four PLCs, which is also the dis-
tance between the breaks of the X4 lines. Therefore,
each X4 line will cross exactly one set of subquad lines.
Since all X4 lines make the same connections to the
subquad lines that they cross, all X4 lines in the array
have the same connectivity, and the symmetry of the
routing is preserved. Since all XH lines cross the same
number of subquad blocks, the symmetry is maintained
for the XH lines as well.
The new subquad lines travel a length of eight PLCs
(seven PLCs on the outside edge) before they are bro-
ken. Unlike other inter-PLC lines, they cannot be con-
nected end-to-end. As shown in Figure 30, some of the
horizontal (vertical) subquad lines have connectivity to
the subquad to the left of (above) the current subquad,
while others have connectivity to the subquad to the
right (below). This allows connections to/from the cur-
rent subquad from/to the PLCs in all subquads that sur-
round it.
Between all subquads, including in the center of the
array, there are three groups of subquad lines where
each group contains four lines. Figure 31 shows the
connectivity of these three groups of subquad lines
(HSUB) to the VX4 and VXH lines running between a
vertical pair of PLCs. Between each vertical pair of
subquad blocks, four of the blocks shown in Figure 31
are used, one for each pair of vertical PLCs.
The first two groups, depicted as A and B, have con-
nectivity to only one of the two sets of X4 lines between
pairs of PLCs. Since they are very lightly loaded, they
are very fast. The third group, C, connects to both
groups of X4 lines between pairs of PLCs, as well as all
of the XH lines between pairs of PLCs, providing high
flexibility. The connectivity for the vertical subquad rout-
ing (Vsub) is the same as described above for the hori-
zontal subquad routing, when rotated onto the other
axis.
At the center row and column of each quadrant, a
fourth group of subquad lines has been added. These
subquad lines only have connectivity to the XH lines.
The XH lines are also broken at this point, which
means that each XH line travels one-half of the quad-
rant (i.e., one-quarter of the device) before it is broken
by a CIP Since the XH lines can be connected end-to-
end, the resulting line can be either one-quarter, one-
half, three-quarters, or the entire length of the array.
The connectivity of the XH lines and this fourth group of
subquad lines, indicated as D, are detailed in Figure
32. Again, the connectivity for the vertical subquad
routing (VSUB) is the same as the horizontal subquad
routing, when rotated onto the other axis.
5-4202(F).r3
Figure 32. Horizontal Subquad Routing
Connectivity (Half Quad)
A
C
B
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
D
B
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[15]
HSUB[14]
HSUB[13]
HSUB[12]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
HSUB[11]
HSUB[10]
HSUB[9]
HSUB[8]
HSUB[15]
HSUB[14]
HSUB[13]
HSUB[12]
HSUB[3]
HSUB[2]
HSUB[1]
HSUB[0]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
HSUB[7]
HSUB[6]
HSUB[5]
HSUB[4]
相關PDF資料 |
PDF描述 |
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| OR2T04A-3S208 | Field-Programmable Gate Arrays |
| OR2T04A-3S208I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 100pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
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相關代理商/技術參數 |
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| OR2T04A-3S84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-3S84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-3T100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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