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參數(shù)資料
| 型號： | OR2C04A |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 197K |
| 代理商： | OR2C04A |
4
Lucent Technologies Inc.
Product Brief
April 1999
ORCASeries 2 FPGAs
Description
(continued)
The ORCAFoundry Development System is used to process a design from a netlist to a configured FPGA. This
system is used to map your design onto the ORCAarchitecture and then place and route it using ORCA Foundry’s
timing-driven tools. The development system also includes interfaces and libraries to popular CAE tools for design
entry, synthesis, and simulation. Some examples of the resources required and the performance that can be
achieved using these devices are represented in Table 2.
The FPGA’s functionalitiy is determined by internal configuration RAM. The FPGA’s internal initialization/configura-
tion circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of
several configuration modes. The configuration data resides externally in an EEPROM, EPROM, or ROM on the
circuit board, or any other storage media. Serial ROMs provide a simple, low pin count method for configuring
FPGAs, while the peripheral and JTAG configuration modes allow for easy, in-system programming (ISP).
Table 2. ORCA Series 2 System Performance
1. Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
tiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
7. OR2TxxB available in -7 and -8 speeds only.
Function
#
PFUs
Speed Grade
Unit
-2A
51.0
51.0
-3A
66.7
66.7
-4A
87.0
87.0
-5A
104.2
104.2
-6A
129.9
129.9
-7A
144.9
144.9
-7B
131.6
131.6
-8B
149.3
149.3
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
32 x 16 RAM (synchronous):
Single Port (read and write/cycle)
4
Single Port
5
Dual Port
6
36-bit Parity Check (internal)
32-bit Address Decode (internal)
4
4
MHz
MHz
22
9
44
14.2
41.5
50.5
19.3
55.6
69.0
25.1
71.9
82.0
31.0
87.7
103.1
36.0
107.5
125.0
40.3
122.0
142.9
37.7
103.1
123.5
44.8
120.5
142.9
MHz
MHz
MHz
9
9
16
4
3.25
21.8
38.2
38.2
13.9
12.3
28.6
52.6
52.6
11.0
9.5
36.2
69.0
83.3
9.1
7.5
45.5
86.2
90.9
7.4
6.1
53.8
92.6
92.6
5.6
4.6
62.5
96.2
96.2
5.2
4.3
57.5
97.7
97.7
6.1
4.8
69.4
112.4
112.4
5.1
4.0
MHz
MHz
MHz
ns
ns
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