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參數(shù)資料
| 型號(hào)： | OR2C15A |
| 廠(chǎng)商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | OR2C15A |
Product Brief
April 1999
ORCA
Series 2
Field-Programmable Gate Arrays
Features
I
High-performance, cost-effective, low-power
0.35 μm CMOS technology (OR2CxxA), 0.3 μm CMOS
technology (OR2TxxA), and 0.25 μm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
I
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
I
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
I
Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
I
Eight 3-state buffers per PFU for on-chip bus structures
I
Fast on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
I
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
I
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
I
Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
I
Enhanced
cascadable
nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
Table 1. ORCA Series 2 FPGAs
I
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
I
Upward bit stream compatible from the ORCAATT2Cxx/
ATT2Txx series of devices
I
Pinout-compatible with new ORCASeries 3 FPGAs
I
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
I
Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source
I
Built-in boundary scan (IEEE
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
I
Full PCI bus compliance for all devices
I
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ORCAFoundry
Development System support (for back-end implementa-
tion)
I
New added features (OR2TxxB) provide:
— More I/O per package than the OR2TxxA family.
— No dedicated 5 V supply (VDD5).
— Faster configuration speed (40 MHz).
— Full PCI bus compliance in both 5 V and 3.3 V PCI
systems. Pin selectable I/O clamping diodes provide
5 V or 3.3 V PCI compliance and 5 V tolerance.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
Device
Usable
Gates*
LUTs
Registers
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
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相關(guān)代理商/技術(shù)參數(shù) |
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| OR2C15A3BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3M84I-D | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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