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參數(shù)資料
| 型號： | OR2C04A |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 197K |
| 代理商： | OR2C04A |
2
Lucent Technologies Inc.
Product Brief
April 1999
ORCASeries 2 FPGAs
Description
The ORCA Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest ORCA series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
ments for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
series are provided in Table 1. All devices are offered in
a variety of packages, speed grades, and temperature
ranges.
ORCA FPGAs consist of two basic elements: program-
mable logic cells (PLCs) and programmable input/out-
put cells (PICs). An array of PLCs is surrounded by
PICs as shown in Figure 1. Each PLC contains a pro-
grammable function unit (PFU). The PLCs and PICs
also contain routing resources and configuration RAM.
All logic is done in the PFU. Each PFU contains four
16-bit look-up tables (LUTs) and four latches/flip-flops
(FFs).
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can be programmed to real-
ize any four-, five-, or six-input logic functions. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, the multiplier function, or the enhanced data
path functions. In memory mode, the LUTs can be
used as a 16 x 4 read/write or read-only memory
(asynchronous mode or synchronous mode) or a 16 x
2 dual-port memory.
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and ver-
tical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
Each PIC (shown in Figures 2A and 2B) is comprised
of I/O drivers, I/O pads, and routing resources. Each
I/O can be programmed to be either an input, output, or
bidirectional signal. Other options include variable out-
put slew rates and pull-up or pull-down resistors.
OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow
interconnection to both 3.3 V and 5 V devices, select-
able on a per-pin basis.
5-4573(F)
Figure 1. PFU Block Diagram
A4
A3
A2
A1
A4
A3
A2
A1
QLUT3
A0
CARRY
CARRY
A3
A2
A1
A0
QLUT2
B4
B3
B2
B1
B4
B3
B2
B1
QLUT1
B0
CARRY
CARRY
B3
B2
B1
B0
QLUT0
CIN
C0
LSR
GSR
WD[3:0]
CK
CKEN
TRI
PFU_XOR
B4
A4
PFU_NAND
PFU_MUX
C
C
C
C
WD3
WD2
WD1
WD0
C
C
C
T
T
T
T
REG3
SR
EN
REG2
SR
EN
REG1
SR
EN
REG0
SR
EN
O4
O3
O2
O1
O0
F3
C
C
COUT
F2
F1
F0
D0
D1
D2
D3
Q0
Q1
Q2
Q3
C
T
T
T
T
C
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