參數(shù)資料
型號： NX25P16-VSI
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 16M X 1 FLASH 2.7V PROM, PDSO8
封裝： 0.208 INCH, SOIC-8
文件頁數(shù)： 43/43頁
文件大小： 918K
代理商： NX25P16-VSI
W25P80 / W25P16 / W25P32
Publication Release Date: December 11, 2005
- 9 -
Revision J
8. FUNCTIONAL DESCRIPTION
8.1 SPI OPERATIONS
8.1.1
SPI Modes
The W25P80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3
concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
8.1.2
HOLD Function
The /HOLD signal allows the W25P80/16/32 operation to be paused while it is actively selected (when
/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are
shared with other devices. For example, consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the
full duration of the /HOLD operation to avoid resetting the internal logic state of the device.
8.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
W25P80/16/32 provides several means to protect data from inadvertent writes.
8.2.1
Write Protect Features
Device resets when VCC is below threshold.
Time delay write disable after Power-up.
Write enable/disable instructions.
Automatic write disable after program and erase.
Software write protection using Status Register.
Hardware write protection using Status Register and /WP pin.
Write Protection using Power-down instruction.
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