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參數(shù)資料
| 型號(hào)： | NX25P16-VSI |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | PROM |
| 英文描述： | 16M X 1 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.208 INCH, SOIC-8 |
| 文件頁(yè)數(shù)： | 25/43頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | NX25P16-VSI |
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W25P80 / W25P16 / W25P32
Publication Release Date: December 11, 2005
- 31 -
Revision J
9.2.18 Erase Parameter Page (D5h)
The Erase Parameter Page instruction sets all 256 bytes of memory in the Parameter Page to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept
the Erase Parameter Page instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the /CS pin low and shifting the instruction code “D5h”. The Erase Parameter Page
instruction sequence is shown in figure 21.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Erase
Parameter Page instruction will not be executed. After /CS is driven high, the self-timed Erase
Parameter Page instruction will commence for a time duration of tPE (See AC Characteristics). While
the Erase Parameter Page cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Erase Parameter Page
cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After
the Erase Parameter Page cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Erase Parameter Page instruction will not be executed if any page is protected by
the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory Protection table).
Figure 21. Parameter Page Erase Instruction Sequence Diagram
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