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參數(shù)資料
| 型號(hào)： | NIMD6302R2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | HDPlus Dual N-Channe Self-protected Field Effect Transistors with 1:200 Current Mirror FET |
| 中文描述： | 6500 mA, 30 V, 4 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | CASE 751-07, SOIC-8 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 97K |
| 代理商： | NIMD6302R2 |
NIMD6302R2
http://onsemi.com
7
3.5
4.00E–01
0
I
S
,
V
SD
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
V
GS
= 0 V
T
J
= 25
°
C
6.00E–01
8.00E–01
1.00E+00
0.5
1
1.5
2
2.5
3
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25
°
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance –
General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded, and that the
transition time (t
r
, t
f
) does not exceed 10 s. In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
– T
C
)/(R
JC
).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non–linearly with an increase of peak current in avalanche
and peak junction temperature.
100
10
1
0.1
100
10
1
0.1
0.01
I
D
,
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
V
GS
= 10 V
SINGLE PULSE
T
C
= 25
°
C
dc
10 ms
Mounted on 2
″
sq. FR4 board (1
″
sq. 2 oz. Cu 0.06
″
thick single sided) with one die operating, 10s max.
1 ms
100 s
10 s
150
75
50
25
300
200
150
50
0
E
A
,
A
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
TJ, STARTING JUNCTION TEMPERATURE (
°
C)
100
250
100
125
I
D
= 15 A
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| NIMD6302R2/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HDPlus Dual N-Channel Self-Protected Field Effect Transistor with 1:200 Current Sense FET |
| NIMD6302R2_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:HDPlus Dual N−Channel Self−protected Field Effect Transistors with 1:200 Current Mirror FET |
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