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參數(shù)資料
| 型號： | NE555N |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 0K |
| 描述： | IC OSC MONO TIMING 8-DIP |
| 標準包裝： | 50 |
| 類型： | 555 型，計時器/振蕩器（單路） |
| 電源電壓： | 4.5 V ~ 16 V |
| 電流 - 電源： | 7.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 供應商設(shè)備封裝： | 8-DIP |
| 安裝類型： | 通孔 |
| 其它名稱： | NE555NFS |
LM555
—
Single
T
imer
2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
LM555 Rev. 1.1.0
5
1. Monostable Operation
Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage
falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low,
the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging
the external capacitor C1 and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and
reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant
RAC, the longer it takes for the VC1 to reach 2 VCC/3. In other words, the time constant RAC controls the output pulse
width.
When the applied voltage to the capacitor C1 reaches 2 VCC/3, the comparator on the trigger terminal resets the flip-
flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-
tionship based on RA and C. Figure 4 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of VCC/3 before
the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied
while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at
the end of the output pulse remains at below VCC/3. Figure 5 shows such a timer output abnormality.
2. Astable Operation
Figure 5. Waveforms of Monostable Operation
(abnormal)
Figure 6. A Stable Circuit
Figure 7. Capacitance and Resistance vs. Frequency
1
5
6
7
8
4
2
3
RESET
Vcc
DISCH
THRES
CONT
GND
OUT
TRIG
+Vcc
RA
C1
C2
RL
RB
100m
1
10
100
1k
10k
100k
1E-3
0.01
0.1
1
10
100
10M
Ω
1M
Ω
100
kΩ
10k
Ω
1kΩ
(R
A+2RB)
Ca
p
a
ci
ta
nc
e(
uF)
Frequency(Hz)
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