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參數(shù)資料
| 型號： | NE555N |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC MONO TIMING 8-DIP |
| 標準包裝： | 50 |
| 類型： | 555 型，計時器/振蕩器（單路） |
| 電源電壓： | 4.5 V ~ 16 V |
| 電流 - 電源： | 7.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 供應(yīng)商設(shè)備封裝： | 8-DIP |
| 安裝類型： | 通孔 |
| 其它名稱： | NE555NFS |
LM555
—
Single
T
imer
2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
LM555 Rev. 1.1.0
4
Application Information
Table 1 below is the basic operating table of 555 timer.
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold volt-
age or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes accord-
ing to threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis-
charge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer
output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt-
age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output
again at high.
1. Monostable Operation
Table 1. Basic Operating Table
Reset
(PIN 4)
VTR
(PIN 2)
VTH
(PIN 6)
Output
(PIN 3)
Discharging
Transistor
(PIN 7)
Low
X
Low
ON
High
< 1/3 VCC
XHigh
OFF
High
> 1/3 VCC
> 2/3 VCC
Low
ON
High
> 1/3 VCC
< 2/3 VCC
Previous State
Figure2. Monostable Circuit
Figure 3. Resistance and Capacitance vs.
Time Delay (tD)
Figure 4. Waveforms of Monostable Operation
1
5
6
7
8
4
2
3
RESET
Vcc
DISCH
THRES
GND
OUT
TRIG
+Vcc
RA
C1
C2
RL
Trigger
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
M
Ω
1M
Ω
10k
Ω
100k
Ω
R A
=1k
Ω
Ca
pa
cit
a
nce(
u
F
)
Time Delay(s)
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