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| 型號： | NCV1124DG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 0K |
| 描述： | IC SENSOR DUAL VAR-RELUCT 8-SOIC |
| 標準包裝： | 98 |
| 類型： | 可變磁阻 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 雙，串聯(lián)或并聯(lián) |
| 電流 - 電源： | 5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOICN |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1131 (CN2011-ZH PDF) |
| 其它名稱： | NCV1124DG-ND NCV1124DGOS |
NCV1124
http://onsemi.com
4
THEORY OF OPERATION
NORMAL OPERATION
Figure 2 shows one channel of the NCV1124 along with
the necessary external components. Both channels share the
INAdj pin as the negative input to a comparator. A brief
description of the components is as follows:
VRS Ideal sinusoidal, ground referenced, sensor output
amplitude usually increases with frequency, depending on
loading.
RRS Source impedance of sensor.
R1/RAdj External resistors for current limiting and
biasing.
INP1/INAdj Internal current sources that determine trip
points via R1/RAdj.
COMP1 Internal comparator with builtin hysteresis
set at 160 mV.
OUT1 Output 0 V 5.0 V square wave with the same
frequency as VRS.
By inspection, the voltage at the (+) and () terminals of
COMP1 with VRS = 0V are:
V+
+ INP1(R1 ) RRS)
(1)
V
+ INAdj
RAdj
(2)
As VRS begins to rise and fall, it will be superimposed on
the DC biased voltage at V+.
V+
+ INP1(R1 ) RRS) ) VRS
(3)
To get comparator COMP1 to trip, the following
condition is needed when crossing in the positive direction,
V+
u V ) VHYS
(4)
(VHYS is the builtin hysteresis set to 160 mV), or when
crossing in the negative direction,
V+
t V * VHYS
(5)
Combining equations 2, 3, and 4, we get:
INP1(R1
) RRS) ) VRS u INAdj
RAdj ) VHYS (6)
therefore,
VRS(+TRP) t INAdj
RAdj * INP1(R1 ) RRS) ) VHYS
(7)
It should be evident that tripping on the negative side is:
VRS(TRP) t INAdj
RAdj * INP1(R1 ) RRS) * VHYS
(8)
In normal mode,
INP1
+ INAdj
(9)
We can now rewrite equation (7) as:
VRS(+TR) u INP1(RAdj * R1 * RRS) ) VHYS (10)
By making
RAdj + R1 ) RRS
(11)
you can detect signals with as little amplitude as VHYS.
A design example is given in the applications section.
OPEN SENSOR PROTECTION
The NCV1124 has a DIAG pin that when pulled high (5.0
V), will increase the INAdj current source by roughly 50%.
Equation (7) shows that a larger VRS(+TRP) voltage will be
needed to trip comparator COMP1. However, if no VRS
signal is present, then we can use equations 1, 2, and 4
(equation 5 does not apply in this mode) to get:
INP1(R1
) RRS) u INP1
KI
RAdj ) VHYS (12)
Since RRS is the only unknown variable we can solve for
RRS,
RRS +
INP1
KI
RAdj ) VHYS
INP1
* R1
(13)
Equation (13) shows that if the output switches states
when entering the diag mode with VRS = 0, the sensor
impedance must be greater than the above calculated value.
This can be very useful in diagnosing intermittent sensor.
INPUT PROTECTION
As shown in Figure 2, an active clamp is provided on each
input to limit the voltage on the input pin and prevent
substrate current injection. The clamp is specified to handle
±12 mA. This puts an upper limit on the amplitude of the
sensor output. For example, if R1 = 20 k, then
VRS(MAX) + 20 k
12 mA
+ 240 V
Therefore, the VRS(pkpk) voltage can be as high as 480 V.
The NCV1124 will typically run at a frequency up to 1.8
MHz if the input signal does not activate the positive or
negative input clamps. Frequency performance will be
lower when the positive or negative clamps are active.
Typical performance will be up to a frequency of 680 kHz
with the clamps active.
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