參數(shù)資料
型號(hào): NCP5331
廠商: ON SEMICONDUCTOR
英文描述: Two-Phase PWM Controller with Integrated Gate Drivers
中文描述: 兩相PWM控制器,帶有集成門極驅(qū)動(dòng)器
文件頁數(shù): 33/38頁
文件大?。?/td> 424K
代理商: NCP5331
NCP5331
http://onsemi.com
33
First, use Equation 15 to calculate the voltage across the
output inductor due to the 52 A load current being shared
equally between the two phases.
(15)
VLo
VIN
VCORE,NO- LOAD
(IO,MAX2)
ESROUTNOUT
12 V
1.575 V
52 A 2
19 m
6
10.51 V
Second, use Equation 16 to determine the rate of current
increase in the output inductor when the load is applied (i.e.,
Lo has decreased to 88% due to the dc current).
dILodt
VLoLo
10.51 V 729 nH
14.4 V
s
(16)
Finally, use Equation 17 and Equation 18 to calculate the
minimum input inductance value.
VCi
ESRINNIN
13 m
dILodt
14.4 V
D fSW
0.146 200 kHz
5
s
28 mV
(17)
LiMIN
VCi
28 mV 0.50 A
dIINdtMAX
s
55 nH
(18)
Next, choose the small, cost effective
T30-26
core from
Micrometals (33.5 nH/N
2
) with #16 AWG. The design
requires only 1.28 turns to achieve the minimum inductance
value. We allow for inductance “swing” at full-load by
using three turns. The input inductor’s value will be
Li
32
33.5 nH N2
301 nH
This inductor is available as part number CTX15-14771
from Coiltronics.
5. MOSFET & Heatsink Selection
For the upper MOSFET we choose two (1) NTD60N03
and for the lower MOSFETs we choose two (2) NTD80N02,
both are from ON Semiconductor. The following parameters
are derived from the data sheets.
NCP5331 Parameter
Value
Gate Drive Current
1.5 A for 1.0
μ
s
Upper Gate Voltage
6.5 V
Lower Gate Voltage
11.5 V
Gate Nonoverlap Time
65 ns
Parameter
NTD60N03
NTD80N02
R
DS(on)
8.0 m
@ 6.5 V
5.0 m
@ 10 V
Q
SWITCH
Q
RR
Q
OSS
V
F,diode
θ
JC
27 nC
26 nC
43 nC
36 nC
12 nC
12 nC
0.75 V @ 2.3 A
0.92 V @ 20 A
1.65
°
C/W
1.65
°
C/W
The rms value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, I
LMAX
, and I
LMIN
at the converter’s maximum
output current.
0.097
[(29.62
29.6
22.4
22.42) 3]1 2
(20)
IRMS,CNTL
[D
(ILo,MAX2
ILo,MIN2) 3]1 2
ILo,MAX
ILo,MIN
2.53 ARMS
Equation 19 is used to calculate the power dissipation of
the control MOSFET but has been modified for one upper
and two lower MOSFETs.
PD,CONTROL
{(IRMS,CNTL2)
QswitchIg
Qoss2
RDS(on)}
VIN
fSW)
(ILo,MAX
(3
fSW)
(VIN
VIN
QRR
fSW)
(19)
{2.532ARMS
(29.6 A
8.0 m }
27 nC 1.5 A
12 V
200 kHz)
(3
12 nC 2
12 V
200 kHz)
(12 V
43 nC
200 kHz)
0.051 W
1.48 W per FET
1.28 W
0.043 W
0.10 W
The rms value of the current in the synchronous MOSFET
is calculated from Equation 27 and the previously derived
values for D, I
Lo,MAX
, and I
Lo,MIN
at the converter’s
maximum output current.
(27)
IRMS,SYNCH
(ILo,MAX2
[(1
D)
ILo,MAX
[(29.62
ILo,MIN
ILo,MIN2) 3]1 2
22.42) 3]1 2
(1
0.097)
29.6
22.4
23.5 ARMS(shared by two synchronous MOSFETs)
Equation 26 is used to calculate the power dissipation of
each synchronous MOSFET. Note: The rms current is
shared by the two lower MOSFETs so the total rms current
is divided by two in the following equation. Also, during the
nonoverlap time, the per-phase current is shared by two
body diodes so the full load current is divided between two
phases and two forward body diodes per phase.
PD,SYNCH
(IRMS,SYNCH2
(Vfdiode
IO,MAX2
(23.5 2)2ARMS
RDS(on))
t_nonoverlap
fSW)
(26)
5.0 m
0.92 V
(52 A 2 2)
65 ns
200 kHz
0.69 W
0.16 W
0.85 W per FET
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