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參數(shù)資料
| 型號： | NCP5331 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Two-Phase PWM Controller with Integrated Gate Drivers |
| 中文描述： | 兩相PWM控制器，帶有集成門極驅(qū)動器 |
| 文件頁數(shù)： | 20/38頁 |
| 文件大小： | 424K |
| 代理商： | NCP5331 |
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NCP5331
http://onsemi.com
20
During no load conditions the V
DRP
pin is at the same
voltage as the V
FB
pin, so none of the V
FB
bias current flows
through the V
DRP
resistor. When output current increases
the V
DRP
pin increases proportionally and the V
DRP
pin
current offsets the V
FB
bias current and causes the output
voltage to decrease.
The response during the first few microseconds of a load
transient are controlled primarily by power stage output
impedance and the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal (external ramp) size is too large or the error
amp too slow there will be a long transition to the final
voltage after a transient. This will be most apparent with
lower capacitance output filters.
Error Amp Compensation, Tuning, and Soft Start
The transconductance error amplifier requires a
capacitance (C
C1
+ C
C2
in the Applications Diagram)
between the COMP pin and GND for two reasons. First, this
capacitance stabilizes the transconductance error amplifier.
Values less than a few nF may cause oscillations of the
COMP voltage and increase the output voltage jitter.
Second, this capacitance sets the soft start and hiccup mode
slopes. The internal error amplifier will source
approximately 30
μ
A during soft start and hiccup mode. No
switching will occur until the COMP voltage exceeds the
Channel Startup Offset (nominally 0.6 V). If C
C2
is set to
0.1
μ
μ
A from the error amplifier will allow the
output to ramp up or down at approximately 30
μ
A/0.1
μ
F
or 0.3 V/ms or 1.2 V in 4 ms.
The COMP voltage will ramp up to the following value.
VCOMP
VCORE@ 0 A
Int_Ramp
Channel_Startup_Offset
GCSA
Ext_Ramp 2
The COMP pin will disable the converter when pulled
below the COMP Discharge Threshold (nominally 0.27 V).
The RC network between the COMP pin and the soft start
capacitor (R
C1
, C
C1
) allows the COMP voltage to slew
quickly during transient loading of the converter. Without
this network the error amplifier would have to drive the large
soft start capacitor (C
C2
) directly, which would drastically
limit the slew rate of the COMP voltage. The R
C1
/C
C1
network allows the COMP voltage to undergo a step change
of approximately R
C1
I
COMP
.
The capacitor (C
A1
) between the COMP pin and the error
amplifier’s inverting input (the V
FB
pin) and the parallel
combination of the resistors R
F1
and R
DRP
determine the
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the R
F1
resistor (C
F1
) adds a zero
to boost phase near the crossover frequency to improve loop
stability.
Figure 26. Power Good Delay Operation
NOTE:
The PGD timer insures that PGD will transition high
when V
CORE
is in regulation.
Setting up and tuning the error amplifier is a three step
process. First, the no-load and full-load adaptive voltage
positioning (AVP) are set using R
F1
and R
DRP
, respectively.
Second, the current sense time constant and error amplifier
gain are adjusted with RSx and C
A1
while monitoring
V
CORE
during transient loading. Lastly, the peak-to-peak
voltage ripple on the COMP pin is examined when the
converter is fully loaded to insure low output voltage jitter.
The exact details of this process are covered in the Design
Procedure section.
Undervoltage Lockout (UVLO)
The controller has undervoltage lockout comparators
monitoring two pins. One, intended for the logic and
low-side drivers, is connected to the V
CCL
pin with an 8.5 V
turn-on and 6.15 V turn-off threshold. A second, for the
high side drivers, is connected to the V
CCH
pin with an 8.5 V
turn-on and 6.75 V turn-off threshold. A UVLO fault sets
the fault latch which forces switching to stop and the upper
and lower gate drivers produce a logic low (i.e., all the
MOSFETs are turned OFF). Power good (PGD) is pulled
low when UVLO occurs. The overcurrent/overvoltage latch
is reset by the UVLO signal.
Power Good (PGD) Delay Time
When V
CORE
is less than the power good threshold,
87.5%
DAC, or greater than 2.0 V the open-collector
power good pin (PGD) will be pulled low by the NCP5331.
When V
CORE
is in regulation PGD will become high
impedance. An external pull-up resistor is required on PGD.
During soft start, when V
CORE
reaches the power good
threshold, 87.5%
DAC, then the “l(fā)onger” of two timers will
dictate when PGD becomes high impedance. One timer is
internally set to 200
μ
s and can not be changed. Placing a
capacitor from the C
PGD
pin to GND sets the second
programmable timer. When V
CORE
crosses the PGD
threshold, a current source will charge C
PGD
starting at
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP5331/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two Phase PWM Controller with Integrated Gate Drivers |
| NCP5331_05 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase PWM Controller with Integrated Gate Drivers |
| NCP5331FTR2 | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5331FTR2G | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate Drivers for Athlon RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5332A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC |
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