參數(shù)資料
型號: NCN6001DTBR2G
廠商: ON Semiconductor
文件頁數(shù): 33/36頁
文件大?。?/td> 0K
描述: IC INTERFACE SMART CARD 20TSSOP
標準包裝: 1
應(yīng)用: 智能卡
接口: 微控制器
電源電壓: 2.75 V ~ 5.5 V
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標準包裝
安裝類型: 表面貼裝
其它名稱: NCN6001DTBR2GOSDKR
NCN6001
http://onsemi.com
6
PIN FUNCTIONS AND DESCRIPTION
TSSOP
Description
Type
Name
LLGA
18
15
CRD_DET
INPUT
The signal coming from the external card connector is used to detect the presence of
the card. A builtin pullup low current source biases this pin High, making it active
LOW, assuming one side of the external switch is connected to ground. A builtin
digital filter protect the system against voltage spikes present on this pin.
The polarity of the signal is programmable by the MOSI message, according to the
logic state depicted Table 2. On the other hand, the meaning of the feedback
message contained in the MISO register bit b4, depends upon the SPI mode of
operation as defined here below:
SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the
polarity of the card detect switch.
SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as
depicted here below, whatever be the polarity of the switch used to handle the
detection:
CRD_DET = Low MISO/b4 = Low
CRD_DET = High MISO/b4 = High
In both cases, the chip must be programmed to control the right logic state (Table 2).
Since the bias current supplied by the chip is very low, typically 5.0 mA, care must be
observed to avoid low impedance or cross coupling when this pin is in the Open state.
19
16
CRD_RST
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator
adapts the RESET signal from the microcontroller to the external card. The output
current is internally limited to 15 mA.
The CRD_RST is validated when CS = Low and hard wired to Ground when the card
is deactivated, by and internal active pull down circuit.
Care must be observed, at PCB design level, to avoid cross coupling between this
signal and the CRD_CLK clock.
20
17
CRD_IO
I/O
Pullup
This pin handles the connection to the serial I/O pin of the card connector. A
bidirectional level translator adapts the serial I/O signal between the card and the
microcontroller. An internal active pull down MOS device forces this pin to Ground
during either the CRD_VCC startup sequence, or when CRD_VCC = 0 V. The
CRD_IO pin current is internally limited to 15 mA.
Care must be observed, at PCB design level, to avoid cross coupling between this
signal and the CRD_CLK clock.
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