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參數(shù)資料
| 型號(hào)： | NB100LVEP224FAR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | NB100LVEP224FAR2G |
NB100LVEP224
http://onsemi.com
7
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
NB100LVEP224
The NB100LVEP224 uses a thermally enhanced 64-lead
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP224 high-speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the
package
and
electrical
performance
of
the
NB100LVEP224. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
The
recommended
thermal
land
design
for
NB100LVEP224 applications on multi-layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 7 providing an efficient heat removal path.
Figure 7. Recommended Thermal Land Pattern
All Units mm
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
4.6
The via diameter should be approximately 0.3 mm with
1oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 8, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 8. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
Figure 8. Recommended Solder Mask Openings
All Units mm
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
4.6
0.2
1.0
0.2
Proper thermal management is critical for reliable system
operation. This is especially true for high-fanout and high
output drive capability products.
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided:
Table 9. Thermal Resistance *
lfpm
qJA 5C/W
qJC 5C/W
0
35.6
3.2
100
32.8
4.9
500
30.0
6.4
* Junction to ambient and Junction to board, four-conductor
layer test board (2S2P) per JESD 51-8
These recommendations are to be used as a guideline,
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP224 package is electrically shorted to the
substrate of the integrated circuit and VEE. The thermal land
should be electrically connected to VEE.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB100LVEP224FARG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 BBG DIF ECL PECL CLD DRV RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB100LVEP56 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:2.5V / 3.3V / 5VECL Dual Differential 2:1 Multiplexer |
| NB100LVEP56/D | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:2.5 V / 3.3 V 5 V ECL Dual Differential 2:1 Multiplexer |
| NB100LVEP56_06 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer |
| NB100LVEP56DT | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 2.5V/3.3V/5V ECL RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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