參數(shù)資料
型號(hào)： NB100LVEP224FAR2G
廠商： ON SEMICONDUCTOR
元件分類： 時(shí)鐘及定時(shí)
英文描述： 100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝： LQFP-64
文件頁數(shù)： 6/10頁
文件大小： 124K
代理商： NB100LVEP224FAR2G
NB100LVEP224
http://onsemi.com
5
Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
Symbol
Characteristic
-40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
IEE
Power Supply Current
VEE = -2.5 V
VEE = -3.3 V
130
140
160
165
195
135
145
165
175
200
205
140
145
165
175
205
210
mA
VOH
Output HIGH Voltage (Note 12)
-1145
-1020
-895
-1145
-1020
-895
-1145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1820
-1600
-1945
-1820
-1600
-1945
-1820
-1600
mV
VIH
Input HIGH Voltage (Single-Ended)
(Note 13)
-1165
-880
-1165
-880
-1165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
(Note 13)
-1945
-1600
-1945
-1600
-1945
-1600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14) (Figure 5)
VEE + 1.2
0.0
VEE + 1.2
0.0
VEE + 1.2
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
CLK
0.5
-150
0.5
-150
0.5
-150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. All outputs loaded with 50
W to VCC - 2.0 V. See Figure 6.
13. Single ended input operation is limited VEE ≤ -3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 15)
Symbol
Characteristic
-40
5C
25
5C
85
5C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOpp
Differential Output Voltage
(Figure 3)
fout < 50 MHz
fout < 0.8 GHz
fout < 1.0 GHz
600
750
700
600
525
725
650
575
550
400
700
650
525
mV
tPLH
tPHL
Propagation Delay (Differential Configuration)
CLKx-Qx
CLK_SELx-Qx
500
600
700
800
550
650
800
750
900
650
750
850
1000
1150
ps
tskew
Within-Device Skew (Note 16)
Device-to-Device Skew (Note 17)
20
50
40
300
20
50
40
300
35
100
60
300
ps
tJITTER
Random Clock Jitter (Figure 3) (RMS)
1
5
1
5
1
5
ps
VPP
Input Swing (Differential Configuration)
(Note 19) (Figure 5)
200
800
1200
200
800
1200
200
800
1200
mV
tS
OE Set Up Time (Note 18)
200
ps
tH
OE Hold Time
200
ps
tr/tf
Output Rise/Fall Time
(20%-80%)
100
200
300
100
200
300
150
250
350
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50
W to VCC - 2.0 V. See Figure 6.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions at identical VCC levels.
18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High-to-Low transition ensures outputs remain disabled during
the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock.
19. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
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