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參數(shù)資料
| 型號： | NAND04GR3B3BN1F |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 17/59頁 |
| 文件大小： | 998K |
| 代理商： | NAND04GR3B3BN1F |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
24/59
Copy Back Program
The Copy Back Program operation is used to copy
the data stored in one page and reprogram it in an-
other page.
The Copy Back Program operation does not re-
quire external memory and so the operation is
faster and more efficient because the reading and
loading cycles are not required. The operation is
particularly useful when a portion of a block is up-
dated and the rest of the block needs to be copied
to the newly assigned block.
If the Copy Back Program operation fails an error
is signalled in the Status Register. However as the
standard external ECC cannot be used with the
Copy Back Program operation bit error due to
charge loss cannot be detected. For this reason it
is recommended to limit the number of Copy Back
Program operations on the same data and or to
improve the performance of the ECC.
The Copy Back Program operation requires four
steps:
1.
The first step reads the source page. The
operation copies all 1056 Words/ 2112 Bytes
from the page into the Data Buffer. It requires:
–
one bus write cycle to setup the command
–
4 bus write cycles to input the source page
address
–
one bus write cycle to issue the confirm
command code
2.
When the device returns to the ready state
(Ready/Busy High), the next bus write cycle of
the command is given with the 4 bus cycles to
input the target page address. Refer to Table
11. for the addresses that must be the same
for the Source and Target pages.
3.
Then the confirm command is issued to start
the P/E/R Controller.
The Data Input cycle for modifying the source
page is performed as shown in Figure 14. After a
Copy Back Program operation, a partial-page pro-
gram is not allowed in the target page until the
block has been erased.
See Figure 14. for an example of the Copy Back
Program operation.
A data input cycle to modify a portion or a multiple
distant portion of the source page, is shown in Fig-
Table 11. Copy Back Program x8 Addresses
Note: 1. DD = Dual Die, QD = Quadruple Die.
Table 12. Copy Back Program x16 Addresses
Note: 1. DD = Dual Die, QD = Quadruple Die.
Density
Same Address for Source and
Target Pages
512 Mbit
no constraint
1 Gbit
no constraint
2 Gbit DD(1)
A28
2 Gbit
no constraint
4 Gbit DD
A29
8 Gbit QD(1)
A29,A30
Density
Same Address for Source and
Target Pages
512 Mbit
no constraint
1 Gbit
no constraint
2 Gbit DD(1)
A27
2 Gbit
no constraint
4 Gbit DD(1)
A28
8 Gbit QD(1)
A28,A29
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND512W3B3BN1E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3CN6E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3CZA6E | 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND08GR3B2CZC6T | 1G X 8 FLASH 1.8V PROM, 35 ns, PBGA63 |
| NAND08GR3B3BZC6E | 1G X 8 FLASH 1.8V PROM, 35 ns, PBGA63 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND04GR4B2DWFD | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
| NAND04GR4B2EN6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND04GR4B2EN6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND04GW3B2AN6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 4GBIT 512MX8 25US 48TSOP - Trays |
| NAND04GW3B2BE06 | 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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