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參數(shù)資料
| 型號： | NAND01GR3A1AN1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 15000 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 882K |
| 代理商： | NAND01GR3A1AN1T |
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
28/56
Automatic Page 0 Read at Power-Up
Automatic Page 0 Read at Power-Up is an option
available on all devices belonging to the NAND
Flash 528 Byte/264 Word Page family. It allows
the microcontroller to directly download boot code
from page 0, without requiring any command or
address input sequence. The Automatic Page 0
Read option is particularly suited for applications
that boot from the NAND.
Devices delivered with Automatic Page 0 Read at
Power-Up can have the Chip Enable Don’t Care
option either enabled or disabled. For details on
how to order the different options, refer to Table
Automatic Page 0 Read Description. At power-
up, once the supply voltage has reached the
threshold level, VDDth, all digital outputs revert to
their reset state and the internal NAND device
functions (reading, writing, erasing) are enabled.
The device then automatically switches to read
mode where, as in any read operation, the device
is busy for a time tBLBH1 during which data is trans-
ferred to the Page Buffer. Once the data transfer is
complete the Ready/Busy signal goes High. The
data can then be read out sequentially on the I/O
bus by pulsing the Read Enable, R, signal. Figure
20. and Figure 21. show the power-up waveforms
for devices featuring the Automatic Page 0 Read
option.
Chip Enable Don’t Care Enabled. If the device
is delivered with Chip Enable Don’t Care and Au-
tomatic Page 0 Read at Power-up, only the first
page (Page 0) will be automatically read after the
power-up sequence. Refer to Figure 20..
Chip Enable Don’t Care Disabled. If the device
is delivered with the Automatic Page 0 Read op-
tion only (Chip Enable Don’t Care disabled), the
device will automatically enter Sequential Row
Read mode (Automatic Memory Download) after
the power-up sequence, and start reading Page 0,
Page 1, etc., until the last memory location is
reached, each new page being accessed after a
time tBLBH1.
The Sequential Row Read operation can be inhib-
ited or interrupted by de-asserting E (set to VIH) or
by issuing a command.
Figure 20. Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-Up
Note: 1.
VDDth is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
VDD
W
E
AL
CL
RB
R
I/O
tBLBH1
Data
N
Data
N+1
Data
N+2
Last
Data
Busy
Data Output
from Address N to Last Byte or Word in Page
VDDth (1)
ai08443b
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND01GR3A3AN1T | 128M X 8 FLASH 1.8V PROM, 15000 ns, PDSO48 |
| NAND01GR4A3AZB6F | 64M X 16 FLASH 1.8V PROM, 15000 ns, PBGA63 |
| NAND01GW4A3AN1T | 64M X 16 FLASH 3V PROM, 12000 ns, PDSO48 |
| NAND01GW4A1AZB1E | 64M X 16 FLASH 3V PROM, 12000 ns, PBGA63 |
| NAND256W3A1AV1T | 32M X 8 FLASH 3V PROM, 10000 ns, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND01GR3A2AN1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AN1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AN1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AN1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GR3A2AN6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
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