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參數(shù)資料
| 型號： | MX839DW |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Controlled Analog I/O Processor |
| 中文描述： | 數(shù)字控制的模擬I / O處理器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MX839DW |
Digitally Controlled Analog I/O Processor
5
MX839 PRELIMINARY INFORMATION
1998 MX
x
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
All trademarks and service marks are held by their respective companies.
3 External Components
DV
DD
AV
DD
DV
DD
MOD2 OUT
AV
DD
N/C
V
SS
V
BIAS
MOD1 OUT
MOD2 IN
MOD1 IN
IRQ
XTAL
SERIAL CLOCK
COMMAND DATA
REPLY DATA
C-BUS
INTERFACE
XTAL/CLOCK
MX839
C3
R3
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
XTAL
DACOUT3
DACOUT2
DACOUT1
N/C
ADCIN1
ADCIN2
ADCIN3
ADCIN4
XTAL/CLOCK
C2
C1
X1
R1
C6
DV
DD
R2
C4
C5
Figure 2: Recommended External Components
R1
R2
R3
C1
C2
C3
1M
:
22k
:
10
:
22pF
22pF
0.1μF
±5%
±10%
±10%
±20%
±20%
±20%
C4
C5
C6
Note 1
0.1μF
0.1μF
10.0μF
±20%
±20%
±20%
Note 1
Note 1
X1
Note 2, 3
±100ppm
Table 1: Recommended External Components
Notes:
1. These values should be determined in regard to the amount of supply filtering required for D/A outputs.
2. If an external clock is to be used, then it should be connected to Pin 2 and the components C1, C2, R1, and X1
omitted. The ADC clock frequency is derived from the crystal or external clock by means of internal programmable
dividers. See Section 6 for details of crystal or external clock frequency range.
3. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of
V
DD
, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design
assistance, consult your crystal manufacturer.
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