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參數(shù)資料
| 型號： | MX839DW |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Controlled Analog I/O Processor |
| 中文描述： | 數(shù)字控制的模擬I / O處理器 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MX839DW |
Digitally Controlled Analog I/O Processor
18
MX839 PRELIMINARY INFORMATION
1998 MX
x
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
All trademarks and service marks are held by their respective companies.
6.1.4
For the following conditions unless otherwise specified:
DV
DD
= 3.3V to 5.0V, T
AMB
= 25°C
Timing
Parameter
Min.
2.0
Typ.
Max.
Units
μs
t
CSE
t
CSH
t
HIZ
t
CSOFF
t
NXT
t
CK
"CS-Enable to Clock-High"
Last "Clock-High to CS-High"
4.0
μs
"CS-High to Reply Output 3-state"
2.0
μs
"CS-High" Time between transactions
2.0
μs
"Inter-Byte" Time
4.0
μs
"Clock-Cycle" time
2.0
μs
7
7
7
7
7
MSB
3
3
3
3
3
5
5
5
5
5
1
1
1
1
1
6
6
6
6
6
2
2
2
2
2
4
4
4
4
4
0
0
0
0
0
LSB
SERIAL CLOCK
MSB
LSB
COMMAND DATA
REPLY DATA
ADDRESS/COMMAND
BYTE
FIRST DATA BYTE
LAST DATA BYTE
LAST REPLY DATA BYTE
FIRST REPLY DATA BYTE
Logic level is not important
CS
t
CSE
t
CK
t
NXT
t
CSH
t
NXT
t
CSOFF
t
HIZ
Figure 5: 'C-BUS' Timing
Timing Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first,
LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing μC serial interface formats 'C-BUS' compatible ICs are able to work with either polarity
SERIAL CLOCK pulses.
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