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參數(shù)資料
| 型號(hào)： | MUNICH128X |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 8.192M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160 |
| 封裝： | METRIC, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 39/39頁 |
| 文件大?。?/td> | 227K |
| 代理商： | MUNICH128X |
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MUNICH128X
Functional Block Description
Semiconductor Group
9
1997-12-01
3
Functional Block Description
The MUNICH128X provides four independent “cores” as well as global functional blocks
(see Figure 2).
3.1
Core Functional Blocks
Each core consists of dedicated circuitry: Serial PCM Interface Controller, Configuration
and State RAM (CSR), 24/32-channel HDLC Controller with internal Transmit and
Receive Buffers, 64-Channel DMA Controller, and Register Set.
3.1.1
Serial PCM Interface Controller
This block controls both Parallel–to-Serial (Tx) and Serial-to-Parallel (Rx) conversion
and PCM timing. Additionally, this block controls the multiplexing of channels through the
HDLC controller, as well as switching for the test loops.
3.1.2
Configuration and State RAM (CSR)
This block contains internal RAM which maintains the state of each channel. The
Multiplex Control Block of the Serial PCM Interface Controller handles the switching of
the CSR information into and out of the 24/32-channel HDLC Controller.
3.1.3
24/32-channel HDLC Controller
The HDLC Controller performs protocol processing for each channel independently,
based on the CSR information for each channel.
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