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參數(shù)資料
| 型號： | MUNICH128X |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 8.192M bps, LOCAL AREA NETWORK CONTROLLER, PQFP160 |
| 封裝： | METRIC, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 37/39頁 |
| 文件大?。?/td> | 227K |
| 代理商： | MUNICH128X |
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MUNICH128X
General Description
Semiconductor Group
7
1997-12-01
1.2
Differences from the MUNICH32
128-channel capability
Symmetrical Rx and Tx Buffer Descriptor formats for faster switching
Improved Tx idle channel polling process for significantly reducing bus occupancy of
idle Tx channels
Additional PCM modes supported: 3.088 MBit/s, 6.176 MBit/s, 8.192 MBit/s
32 Bit / 33 MHz PCI 2.1 master/slave interface;
this interface can be configured in De-mux mode
Separate Rx and Tx Status Queues in host memory
(the MUNICH128X provides one set for each of the four HDLC Controllers)
Slave access to on-chip registers
Time Slot-shift capability:
– Programmable from -4 clock edges to +3 clock edges
relative to the synchronization pulse
– Programmable to sample Tx and/or Rx data at either falling or rising edge of clock
Software initiated action request (via the Command Register)
Tx End-of-Packet transmitted-on-wire interrupt capability for each channel
Tx packet size increased to 64 Kbytes (HDLC mode)
Rx packet size 8 Kbyte limit interrupt disable
Tx data TRISTATETM control line
Synchronized data transfer in TMA mode
for complete transparency when using fractional T1/PRI
Little/Big Endian data formats
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