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| 型號(hào)： | MU9C1480A-90DC |
| 英文描述： | Content Addressable Memory |
| 中文描述： | 內(nèi)容可尋址存儲(chǔ)器 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 246K |
| 代理商： | MU9C1480A-90DC |
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MU9C1480A/L Draft
Rev. 3.0 Draft
5
related to the destination or source address information
held in the CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary entries,
while the RAM field holds the translations, with almost
instantaneous response.
Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
Empty, Valid, Skip, or RAM. When data is written to the
active Comparand register, and the active Segment Control
register reaches its terminal count, the contents of the
Comparand register are automatically compared with the
CAM portion of all the valid entries in the memory array.
For added versatility, the Comparand register can be
barrel-shifted right or left one bit at a time. A Compare
instruction then can be used to force another compare
between the Comparand register and the CAM portion of
memory entries of any one of the four validity types. After
a Read or Move from Memory operation, the validity bits
of the location read or moved will be copied into the Status
register, where they can be read using Command
Read cycles.
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match or
Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also be
written directly to the memory from the DQ bus using any
of the above addressing modes. The Address register may
be directly loaded and may be set to increment or
decrement, allowing DMA-type reading or writing from
memory.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
typically would be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a single
instruction to change the current set of configuration
registers. The match condition of the device is reset
whenever the active register set is changed.
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning, disable
or select masking conditions, disable or select
auto-incrementing or auto-decrementing the Address
register, and select Standard or Enhanced mode. The active
Segment Control register contains separate counters to
control the writing of 16-bit data segments to the selected
persistent destination, and to control the reading of 16-bit
data segments from the selected persistent source.
There are two active mask registers at any one time, which
can be selected to mask comparisons or data writes. Mask
Register 1 has both a foreground and background mode to
support rapid context switching. Mask Register 2 does not
have this mode, but can be shifted left or right one bit at a
time. For masking comparisons, data stored in the active
selected mask register determines which bits of the
comparand are compared against the valid contents of the
memory. If a bit is set HIGH in the mask register, the same
bit position in the Comparand register becomes a “don’t
care” for the purpose of the comparison with all the memory
locations. During a Data Write cycle or a MOV instruction,
data in the specified active mask register can also determine
which bits in the destination will be updated. If a bit is
HIGH in the mask register, the corresponding bit of the
destination is unchanged.
The match line associated with each memory address is fed
into a priority encoder where multiple responses are
resolved, and the address of the highest-priority responder
(the lowest numerical match address) is generated. In LAN
applications, a multiple response might indicate an error. In
other applications the existence of multiple responders may
be valid.
Four input control signals and commands loaded into an
instruction decoder control the LANCAM. Two of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and
the data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed
using Temporary Command Override instructions. The data
path from the DQ bus to/from data resources (comparand,
masks, and memory) within the device are set until changed
by Select Persistent Source and Destination instructions.
After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register,
FUNCTIONAL DESCRIPTION Continued
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MU9C1480A-90DI | Content Addressable Memory |
| MU9C1480B-50TAC | Content Addressable Memory |
| MU9C1480B-70TAC | Content Addressable Memory |
| MU9C1480B-90TAC | Content Addressable Memory |
| MU9C1480B-90TAI | Content Addressable Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MU9C1480A-90DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480B-50TAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
| MU9C1480B-70TAC | 制造商:MUSIC 制造商全稱:MUSIC Semiconductors 功能描述:LANCAM B Family |
| MU9C1480B-90TAC | 制造商:MUSIC 制造商全稱:MUSIC Semiconductors 功能描述:LANCAM B Family |
| MU9C1480B-90TAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Content Addressable Memory |
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