參數(shù)資料
型號(hào)： MU9C1480A-90DC
英文描述： Content Addressable Memory
中文描述： 內(nèi)容可尋址存儲(chǔ)器
文件頁數(shù)： 19/28頁
文件大小： 246K
代理商： MU9C1480A-90DC
MU9C1480A/L Draft
Rev. 3.0 Draft
19
MNEMONIC FORMAT
INS dst,src[msk],val
INS:
Instruction mnemonic
dst:
Destination of the data
src:
Source of the data
msk:
Mask register used
val:
Validity condition set at the location written
Instruction: Select Persistent Source
Operation
Comparand Register
Mask Register 1
Mask Register 2
Memory Array at Addr. Reg.
Memory Array at Address
Mem. at Highest-Prio. Match
Mnemonic
SPS CR
SPS MR1
SPS MR2
SPS M@[AR]
SPS M@aaaH
SPS M@HM
Op-Code
0000H
0001H
0002H
0004H
0804H
0005H
Instruction: Select Persistent Destination
Operation
Comparand Register
Masked by MR1
Masked by MR2
Mnemonic
SPD CR
SPD CR[MR1]
SPD CR[MR2]
Op-Code
0100H
0140H
0180H
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
Masked by MR2
SPD MR1
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V 0164H
SPD M@[AR][MR2],V 01A4H
0108H
0110H
0124H
Mem. at Addr. Reg. set Empty
Masked by MR1
Masked by MR2
SPD M@[AR],E
SPD M@[AR][MR1],E
SPD M@[AR][MR2],E
0125H
0165H
01A5H
Mem. at Addr. Reg. set Skip
Masked by MR1
Masked by MR2
SPD M@[AR],S
SPD M@[AR][MR1],S 0166H
SPD M@[AR][MR2],S 01A6H
0126H
Mem. at Addr. Reg. set Random SPD M@[AR],R
Masked by MR1
Masked by MR2
0127H
SPD M@[AR][MR1],R 0167H
SPD M@[AR][MR2],R 01A7H
Memory at Address set Valid
Masked by MR1
Masked by MR2
SPD M@aaaH,V
SPD M@aaaH[MR1],V 0964H
SPD M@aaaH[MR2],V09A4H
0924H
Memory at Addr. set Empty
Masked by MR1
Masked by MR2
SPD M@aaaH,E
SPD M@aaaH[MR1],E 0965H
SPD M@aaaH[MR2],E 09A5H
0925H
Memory at Address set Skip
Masked by MR1
Masked by MR2
SPD M@aaaH,S
SPD M@aaaH[MR1],S0966H
SPD M@aaaH[MR2],S 09A6H
0926H
Mem. at Address set Random
Masked by MR1
Masked by MR2
SPD M@aaaH,R
SPD M@aaaH[MR1],R 0967H
SPD M@aaaH[MR2],R09A7H
0927H
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
Masked by MR1
Masked by MR2
012CH
016CH
01ACH
SPD M@HM[MR1],V
SPD M@HM[MR2],V
INSTRUCTION SET SUMMARY
Instruction: Select Persistent Destination Cont.
Operation
Mem. at Highest-Prio. Match, Emp. SPD M@HM,E
Masked by MR1
Masked by MR2
Mnemonic
Op-Code
012DH
016DH
01ADH
SPD M@HM[MR1],E
SPD M@HM[MR2],E
Mem. at Highest-Prio. Match, Skip
Masked by MR1
Masked by MR2
SPD M@HM,S
SPD M@HM[MR1],S
SPD M@HM[MR2],S
012EH
016EH
01AEH
Mem. at High.-Prio. Match, RandomSPD M@HM,R
Masked by MR1
Masked by MR2
012FH
016FH
01AFH
SPD M@HM[MR1],R
SPD M@HM[MR2],R
Mem. at Next Free Addr., Valid SPD M@NF,V
Masked by MR1
Masked by MR2
0134H
0174H
01B4H
SPD M@NF[MR1],V
SPD M@NF[MR2],V
Mem. at Next Free Addr., Empty SPD M@NF,E
Masked by MR1
Masked by MR2
0135H
0175H
01B5H
SPD M@NF[MR1],E
SPD M@NF[MR2],E
Mem. at Next Free Addr., Skip
Masked by MR1
Masked by MR2
SPD M@NF,S
SPD M@NF[MR1],S
SPD M@NF[MR2],S
0136H
0176H
01B6H
Mem. at Next Free Addr., Random SPD M@NF,R
Masked by MR1
Masked by MR2
0137H
0177H
01B7H
SPD M@NF[MR1],R
SPD M@NF[MR2],R
Instruction: Temporary Command Override
Operation
Control Register
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
Mnemonic
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Op-Code
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
Instruction: Data Move
Operation
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
Masked by MR2
Mnemonic
Op-Code
NOP
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
0300H
0301H
0302H
0304H
0344H
0384H
Memory at Address
Masked by MR1
Masked by MR2
MOV CR,aaaH
MOV CR,aaaH[MR1]
MOV CR,aaaH[MR2]
0B04H
0B44H
0B84H
Mask Register 1 from:
Comparand Register
No Operation
Mask Register 2
Memory at Address Reg.
Memory at Address
Mem. at Highest-Prio. Match MOV MR1,HM
MOV MR1,CR
NOP
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
0308H
0309H
030AH
030CH
0B0CH
030DH
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