參數(shù)資料
型號: MTV121
廠商: Electronic Theatre Controls, Inc.
英文描述: Super On-Screen-Display for LCD Monitor
中文描述: 超級屏幕為液晶顯示器面板
文件頁數(shù): 14/18頁
文件大?。?/td> 220K
代理商: MTV121
14/18
MTV121 Revision 5.0 06/29/1999
MTV121
MYSON
TECHNOLOGY
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol
V
IH
Parameter
Input High Voltage
Conditions (Notes)
-
Min.
Max.
VDD+0.3
0.3 * VDD
(0.2 * VDD for SSB
pin)
-
Units
V
0.7 * VDD
V
IL
Input Low Voltage
-
VSS-0.3
V
V
OH
V
OL
Output High Voltage
I
OH
-5 mA
I
OL
5 mA
-
VDD-0.8
V
Output Low Voltage
-
0.5
V
V
ODH
Open Drain Output High
Voltage
(For all OD pins, and pulled
up by external 5 to 9V
power supply)
5 mA
I
DOL
( For all OD pins )
Pixel rate=96MHz
I
load = 0uA
Vin = VDD,
I
load = 0uA
5
9
V
V
ODL
Open Drain Output Low
Voltage
-
0.5
V
I
CC
Operating Current
-
25
mA
I
SB
Standby Current
-
12
mA
Symbol
f
HFLB
T
r
T
f
t
BCSU
t
BCH
t
DCSU
t
DCH
t
SCKH
t
SCKL
t
SU:STA
t
HD:STA
t
SU:STO
t
HD:STO
t
SETUP
t
HOLD
t
pd
PIXin
Parameter
Min.
15
-
-
200
100
200
100
500
500
500
500
500
500
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
130
5
5
-
-
-
-
-
-
-
-
-
-
Units
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HFLB input frequency
Output rise time
Output fall time
SSB to SCK set up time
SSB to SCK hold time
SDA to SCK set up time
SDA to SCK hold time
SCK high time
SCK low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
HFLB delay to rising edge of pixel clock
minimum pulse width of HFLB
propagation delay of output to pixel clock
2
25
6
ns
ns
ns
10
pixel clock input
6
96
MHz
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