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參數(shù)資料
| 型號(hào)： | MTV121 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Super On-Screen-Display for LCD Monitor |
| 中文描述： | 超級(jí)屏幕為液晶顯示器面板 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | MTV121 |
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10/18
MTV121 Revision 5.0 06/29/1999
MTV121
MYSON
TECHNOLOGY
This byte is reserved for internal testing.
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen.
FAN - Enable the fade-in/fade-out function when OSD is turned on from off state or vice verca. The function
roughly takes about one second to fully display the whole menu or to disappear completely.
BLANK - Force the FBKG pin output to high while this bit is set to "1".
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the dis-
playing of characters or windows, otherwise, it outputs only during the displaying of character.
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That
is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins
are in high impedance state. The initial value is 0 after power up.
FBKGP - Select the polarity of the output pin FBKG
= 1
Positive polarity FBKG output is selected.
= 0
Negative polarity FBKG output is selected.
The initial value is 1 after power up.
PWMCK - Select the output options to HTONE/PWMCK pin.
= 0
HTONE option is selected.
= 1
PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB.
The frequency is selected by (PWM1, PWM0) shown as Table 5.
Column 15
b7
b6
b5
b4
Reserved
b3
b2
b1
b0
Column 16
b7
-
b6
-
b5
-
b4
b3
b2
b1
b0
RSPACE
MSBLSB
Column 17
b7
b6
b5
b4
FAN
b3
b2
b1
b0
OSDEN
BSEN
SHADOW
BLANK
WENCLR
RAMCLR
FBKGC
Column 18
B7
TRIC
b6
b5
b4
b3
HSP
b2
VSP
b1
b0
FBKGP
PWMCK
DWE
PWM1
PWM0
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相關(guān)代理商/技術(shù)參數(shù) |
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| MTV1-21PL1 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-21PL1 - Bulk |
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| MTV1-21SAL1 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-21SAL1 - Bulk |
| MTV1-21SH001 | 制造商:ITT Interconnect Solutions 功能描述:MTV1-21SH001 - Bulk |
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