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參數(shù)資料
| 型號(hào)： | MTV012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Mask Version |
| 中文描述： | CRT顯示器8051嵌入式控制器掩模版 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | MTV012A |
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MYSON
TECHNOLOGY
MTV012A
MTV012A Revision 1.1 12/23/1998
10/14
status; S/W may clear it by setting CLRDDC. The control bits M128/M256 are used to block the
EEPROM write operation from the host if the address is over 128/256.
5.3 Master Mode IIC Function Block
The master mode IIC block is connected to the ISDA and ISCL pins. The software program can access
the external EEPROM through this interface. Since the EDID/VDIF data and the display information
share the common EEPROM, precaution must be taken to avoid bus conflict. In DDC1 mode, the IIC
interface is controlled by MTV012A only. In DDC2B mode, the host may access the EEPROM directly.
Software can test the HSCL condition by reading the BUSY flag, which is set in case of HSCL=0. A
summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM
1. Write to MBUF the EEPROM slave address (bit 0 = 0).
2. Set S bit to Start.
3. After MTV012A transmits this byte, a MI interrupt will be triggered.
4. The program can write MBUF to transfer the next byte, or set the P bit to stop.
* Please see the attachments about "Master IIC Transmission Timing".
5.3.2. To Read EEPROM
1. Write to MBUF the slave address (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV012A transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out to MBUF the useless byte in order to continue the data transfer.
6. After MTV012A receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but the P bit needs to be set before reading
can terminate the operation.
* Please see the attachments about the "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL pins or ISDA/ISCL pins, and selected by the
SLVsel control bit. This block is receiving mode only. S/W may set the SLVADR register to determine the
address range to which this block should respond. The block first detects an IIC slave address match
condition, then issues a SLVMI interrupt. The data received from SDA is shifted onto the shift register
and moved to the SLVBUF latch. The first byte loaded is the word address (the slave address is
dropped). This block also generates a SLVBI each time the SLVBUF is loaded. If S/W can't read out the
SLVBUF in time, the next byte will not be written to SLVBUF and the slave block returns NACK to the
master. This feature guarantees the data integrity of communication. A WADR flag can tell S/W if the
data in SLVBUF is a word address.
* Please see the attachments about "Slave IIC Block Timing".
6. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip
reset signal. After the power supply is above 4.0V, LVR maintains the reset state for a 144 Xtal cycle to
guarantee that the chip exit reset condition has a stable Xtal oscillation. The specific time of power
supply in the low level is 3us and is adjustable by an external capacitor connected to the RST pin.
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT(2:0). The
timer function is disabled after power-on reset; the user can activate this function by setting WEN, and
clear the timer by setting WCLR.
reg name
MSTUS
MBUF
INTFLG
Addr
00h (r)
10h (r/w)
50h (r/w)
bit7
X
MBUF7
HPRchg
bit6
bit5
DDC2
MBUF5
HPLchg
bit4
BERR
MBUF4
VPLchg
bit3
HFREQ
MBUF3
HFchg
bit2
FIFOH
MBUF2
VFchg
bit1
FIFOL
MBUF1
FIFOI
bit0
BUSY
MBUF0
MI
SCLERR
MBUF6
VPRchg
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTV012E | 8051 Embedded CRT Monitor Controller OTP Version |
| MTV018 | IC TXRX PHY 10/100 3.3V 48LQFP |
| MTV021 | Enhanced Super On-Screen Display |
| MTV021N20 | Enhanced Super On-Screen Display |
| MTV021N24 | Enhanced Super On-Screen Display |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTV012E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller OTP Version |
| MTV016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced On-Screen-Display Controller |
| MTV016N-10 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV016N-18 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV018 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Super On-Screen-Display |
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