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MTD655 Revision 2.0 17/03/2000
MTD655
MYSON
TECHNOLOGY
Note: Asynchronous SRAM acess time: 10/12 ns (max)
RXD4_0
RXD4_1
TXEN4
TXD4_0
TXD4_1
57
58
56
55
54
I
I
Port4 RMII receive data bit_0.
Port4 RMII receive data bit_1.
Port4 RMII transmit enable signal.
Port4 RMII transmit data bit_0.
Port4 RMII transmit data bit_1.
O
O
O
High Speed Asynchronous SRAM Interface Pins
Name
Pin Number
94
106
111,113,115,
118,120,119,
116,114
90,91,93,96,
95,102,108,
100,98,97,99
,101,104,107
,109,110,112
I/O
O
O
I/O ASRAM data bus
Descriptions
WEB
OEB
D[7:0]
ASRAM control pin for write (low active).
ASRAM control pin for read (low active).
A[16:0]
O
ASRAM address bus
10M Inter-Bus Interface pins
Name
Pin Number
I/O
I
Descriptions
IMASTER
67
Master hub selection:
when high: means hub internal inter_bus arbiter is enabled and hub
internal two_port switch is well conneted to 10M_hub core and
100M_hub core .
when low: means hub internal inter_bus arbiter is disabled and hub
internal two_port switch is not connected to 10M_hub core and
100M_hub core.
IACKB10
84
I/O 10M Inter-Bus port access acknowledge signal (low active). For master
hub, this pin is output; for slave hub is input, or while EXT_ARB
jumper was set to “1”, this pin is input from an external arbitration
device.
I/O 10M Inter-Bus collision signal (low active). For master hub, this pin can
output multi hub collision event to inform all slave hub ; for slave hub,
this pin is an input, or while EXT_ARB jumper was set to “1”, this pin
is input from an external arbitration device.
I
10M Inter-Bus port access request input.
I
10M Inter-Bus port access request input.
I
10M Inter-Bus port access request input.
O
10M Inter-Bus port access request output.
ICOLB10
85
IREQ10_IN0
IREQ10_IN1
IREQ10_IN2
IREQ10_OUT
88
87
86
89
RMII Port Interface Pins (port1 ~port4)
Name
Pin Number
I/O
Descriptions