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參數(shù)資料
| 型號： | MTD655 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5 Port 10M/100M Hub With 2 port Switch |
| 中文描述： | 5端口10M/100M自適應(yīng)樞紐2端口開關(guān) |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 197K |
| 代理商： | MTD655 |
4/18
MTD655 Revision 2.0 17/03/2000
MTD655
MYSON
TECHNOLOGY
1.0 PIN DESCRIPTIONS
MII Port Interface Pins (port0)
Name
Pin Number
19
20
27
28
I/O
I
I
I
I
I
I
I
O
O
O
O
O
I
Descriptions
RXD0_0
RXD0_1
RXD0_2
RXD0_3
CRS0
RXDV0
RXCLK0
TXEN0
TXD0_0
TXD0_1
TXD0_2
TXD0_3
TXCLK0
Port0 MII receive data bit_0.
Port0 MII receive data bit_1.
Port0 MII receive data bit_2.
Port0 MII receive data bit_3.
Port0 MII asynchronous carrier indicator from PHY device.
Port0 MII synchronous receive data valid signal from PHY device.
Port0 MII receive clock.
Port0 MII transmit enable signal.
Port0 MII transmit data bit_0.
Port0 MII transmit data bit_1.
Port0 MII transmit data bit_2.
Port0 MII transmit data bit_3.
Port0 MII transmit clock.
30
29
15
18
17
16
10
9
12
RMII Port Interface Pins (port1 ~port4)
Name
Pin Number
33
I/O
I
Descriptions
CRSDV1
Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
Port1 RMII receive data bit_0.
Port1 RMII receive data bit_1.
Port1 RMII transmit enable signal.
Port1 RMII transmit data bit_0.
Port1 RMII transmit data bit_1.
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
Port2 RMII receive data bit_0.
Port2 RMII receive data bit_1.
Port2 RMII transmit enable signal.
Port2 RMII transmit data bit_0.
Port2 RMII transmit data bit_1.
Port3 RMII receive interface signal, CRSDV3 is asserted high when
port3 media is non_idle.
Port3 RMII receive data bit_0.
Port3 RMII receive data bit_1.
Port3 RMII transmit enable signal.
Port3 RMII transmit data bit_0.
Port3 RMII transmit data bit_1.
Port4 RMII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
RXD1_0
RXD1_1
TXEN1
TXD1_0
TXD1_1
CRSDV2
37
38
36
35
34
39
I
I
O
O
O
I
RXD2_0
RXD2_1
TXEN2
TXD2_0
TXD2_1
CRSDV3
43
44
42
41
40
47
I
I
O
O
O
I
RXD3_0
RXD3_1
TXEN3
TXD3_0
TXD3_1
CRSDV4
51
52
50
49
48
53
I
I
O
O
O
I
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