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參數(shù)資料
| 型號(hào)： | MTD655 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5 Port 10M/100M Hub With 2 port Switch |
| 中文描述： | 5端口10M/100M自適應(yīng)樞紐2端口開關(guān) |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 197K |
| 代理商： | MTD655 |
10/18
MTD655 Revision 2.0 17/03/2000
MTD655
MYSON
TECHNOLOGY
REQOUT , but IACKB is asserted, means this MTD655 can get data from IDATA bus. When only one
MTD655 output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master device, If
larger than two MTD655’s REQOUT were asserted, Inter-Bus master will not assert IACKB , but will
assert ICOLB to inform all the connected MTD655s.
The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin’s jumper set-
ting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation.
And in this mode, the stackable capability is not limitted by the MTD655’s REQIN pins number.
2.6 10M/100M packet Switch
The MTD655 inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address
entrys are provided for packets’ SA learning and DA routing; and alsoprovide automatic aging function
( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external
memory first, while packet is good for forward ( CRC chech ok, 64Bytes < length > 1518Bytes, and not
local packets ) , than forward this packet to 100M Hub (or 10M Hub).
2.7 Uplink Switch Port
The MTD655 can config one switch port as an uplink switch port. When UPSWEN pin is high, and
IMASTER pin is low, one of the intenal switch port is connect to 100M HUB, the other is connected to
RMII port 4. In uplink switch mode, port 4 can work in 10M/100M(from SPD4 pin), half/full duplex(from
FD4 pin) mode.
2.8 Memory Interface
The MTD655 use asynchronous SRAM as two port switchs’ packet buffers, total has 128K byte exter-
nal memory for packet buffering.
2.9 MII management
The MTD655 can be managed through MDC, MDIO pins. The MTD655 implements
3
MII registers for
function control and status report (see Section 4.0 on page ).
The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to
5’h1f internally.
2.10 LED display
The MTD655 implements three display modes, port RX activity, 10/100M domain collision, port parti-
tion. The LED data pin LEDDAT is high actived.
One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user
can shift the latched data into byte aligned shift register to drive LEDs.
3.0 Registers
The MTD655 implements
3
MII registers, define as following tables:
TABLE 1. MII registers
REG
NO
0
Bits
Name
R/W
Descriptions
Default
CtlReg0
R/W
CONTROL REGISTER 0
0
1
2
3
4
Reserved.
Set this bit will disable 10M hub core partition function.
Set this bit will disable 100M hub core partition function.
Set this bit will disable 10M hub core Jabber function.
Set this bit will disable 100M hub core Jabber function.
Reserved
Set "1" will program 100M partition cclimit to 128.
1’b0
1’b0
1’b0
1’b0
1’b0
4’b000
1’b0(64)
DisPar10
DisPar100
DisJab10
DisJab100
5-8
9
CClimit100
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