參數(shù)資料
型號: MTC20136PQ-l1
廠商: 意法半導(dǎo)體
英文描述: ADSL TRANSCEIVER CONTROLLER
中文描述: 寬帶收發(fā)器控制器
文件頁數(shù): 20/25頁
文件大?。?/td> 634K
代理商: MTC20136PQ-L1
MTC20136
20/25
Table 8. write cycle timing in parallel modes 0 and 1
Read cycle timing
Figure 9. Ctrl-E interface: read cycle timing in parallel modes 0 and 1
Table 9. read cycle timing in parallel modes 0 and 1
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
Description
Min
0
0
215
15
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
C_A Setup to C_notDS (C_notWr) low
C_notCS, C_Rd/notWr setup to C_notDS (C_notWr) low
C_notDS (C_notWr) pulse width
C_D setup to C_notDS (C_notWr) high
C_A, C_D hold from C_notDS (C_notWr) high
C_notDtAck (C_notRdy) valid from C_notDS (C_notWr) low
C_notDtAck (C_notRdy) tri-state from C_notDS (C_notWr) high
C_notCS, C_Rd/notWr hold from C_notDS (C_notWr) high
C_notCS high to C_notCS Low
15
15
0
100
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Description
Min
0
0
215
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C_A Setup to C_notDS (C_notRd) low
C_notCS, C_Rd/notWr setup to C_notDS (C_notRd) low
C_notDS (C_notRd) pulse width
C_D valid from C_notDtAck (C_notRdy) low
C_A, hold from C_notDS (C_notRd) high
C_notDtAck (C_notRdy) valid from C_notDS (C_notRd) high
C_notDtAck (C_notRdy) tri-state from C_notDS (C_notRd) high
C_notCS, C_Rd/notWr hold from C_notDS (C_notRd) high
Data tri-state from C_notDS (C_notRd) high
Data tri-state from C_notCS high
C_notCS high to C_notCS low (Min. time between 2 Accesses)
10
0
15
10
10
90
5
100
100
15
t1
C_A[8:0]
C_D[7:0]
C_notCS
C_Rd/notWr
C_notDS
C_notDtAck
C_notRd
Mode 0
C_notWr
C_notRdy
t2
t7
t6
t3
t8
t4
t5
t11
t10
t9
Mode 1
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