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參數(shù)資料
| 型號(hào)： | MT9V011P11ST |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR |
| 中文描述： | 4英寸顯卡的CMOS有源像素的數(shù)字圖像傳感器 |
| 文件頁(yè)數(shù)： | 29/33頁(yè) |
| 文件大小： | 537K |
| 代理商： | MT9V011P11ST |
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1/4-INCH VGA CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Preliminary
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
29
2004 Micron Technology, Inc.
Tw o-Wire Serial Bus Timing
The two-wire serial bus operation requires certain
minimum master clock cycles between transitions.
These are specified in the following diagrams in mas-
ter clock cycles.
Figure 22: Serial Host Interface Start
Condition Timing
Figure 23: Serial Host Interface Stop
Condition Timing
NOTE:
All timing are in units of master clock cycle.
Figure 26: Acknow ledge Signal Timing After an 8-bit Write to the Sensor
Figure 24: Serial Host Interface Data
Timing for Write
NOTE:
SDATA is driven by an off-chip transmitter.
Figure 25: Serial Host Interface Data
Timing for Read
NOTE:
SDATA is pulled LOW by the sensor, or allowed to be
pulled HIGH by a pull-up resistor off-chip.
Figure 27: Acknowledge Signal Timing After an 8-bit Read from the Sensor
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is
complete, the master must generate a no acknowledge by leaving SDATA to float high. On the following cycle a start or
stop bit may be used.
SCLK
5
SDATA
4
SCLK
5
SDATA
4
SCLK
4
SDATA
4
SCLK
5
SDATA
SCLK
Sensor pulls down
SDATA pin
6
SDATA
3
SCLK
Sensor tri-states SDATA pin
(turns off pull down)
7
SDATA
6
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