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參數(shù)資料
| 型號： | MT9V011P11ST |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR |
| 中文描述： | 4英寸顯卡的CMOS有源像素的數(shù)字圖像傳感器 |
| 文件頁數(shù)： | 21/33頁 |
| 文件大?。?/td> | 537K |
| 代理商： | MT9V011P11ST |
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1/4-INCH VGA CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Preliminary
09005aef80c6407f
MT9V011_external_DS_2.fm - Rev. A 8/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
21
2004 Micron Technology, Inc.
Feature Description
Window Control
Reg0x01 Row Start, Reg0x02 Column Start,
Reg0x03 Window Height (row size), and Reg0x04
Window Width (column size)
These registers control the size and starting coordi-
nates of the window. By changing these registers, any
image format smaller than or equal to VGA can be
specified.
Blanking Control
Reg0x05 Horizontal Blanking, and Reg0x06 Verti-
cal Blanking
Blanking Control:
These registers control the blanking time in a row
(called column fill-in or horizontal blanking) and
between frames (vertical blanking).
Horizontal blanking is specified in terms of pixel
clocks.
Vertical blanking is specified in terms of row
readout times. (The programmed value is one less
than the actual value.)
The actual imager timing can be calculated using
Table3 on page10 which describes "Row Timing and
FRAME_VALID/LINE_VALID Signals.”
The number of dark rows read out depends on the
vertical blanking set as shown in the Table8.
Pixel Integration Control
Reg0x09 Shutter Width, and Reg0x0C Shutter
Delay
These registers (along with the Window Size and
horizontal blanking registers) control the integration
time for the pixels.
Reg0x09: number of rows of integration, default =
0x01FC (508)
Reg0x0C: reset delay, default = 0x0000 (0). This is the
number of master clocks that the timing and control
logic waits before asserting the reset for a given row.
The actual total integration time,
t
INT, is:
t
INT =
Reg0x09 x Row Time - Overhead time - Reset delay,
where:
Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x
(Reg0x0A + 2) master clock periods
Overhead time = K x 57 master clock periods
Reset delay = K x Reg0x0C master clock periods
If the value in Reg0x0C exceeds (row time - 444)/K
master clock cycles, the row time will be extended by
(K x Reg0x0C - (row time - 444)) clock cycles.
Where :
K = 4 when Reg0x07[4] = 0, and
K = 2 when Reg0x07[4] = 1
In this expression the row time term corresponds to
the number of rows integrated. The overhead time is
the time between the READ cycle and the RESET cycle,
and the final term is the effect of the reset delay.
Typically, the value of Reg0x09 (Shutter Width) is
limited to the number of rows per frame (which
includes vertical blanking rows), such that the frame
rate is not affected by the integration time. If Reg0x09
is increased beyond the total number of rows per
frame, the MT9V011 will add additional blanking rows
as needed. A second constraint is that
t
INT must be
adjusted to avoid banding in the image from light
flicker. Under 60 Hz flicker, this means
t
INT must be a
multiple of 1/120 of a second. Under 50 Hz flicker,
t
INT must be a multiple of 1/100 of a second.
Pixel Clock Speed
Reg0x0A Pixel Clock Speed
The pixel clock speed is set by Reg0x0A. The pixel
clock period will be the number set plus two master
clock cycles. The default value is 0, which is equal to 2
master clock cycles. With a master clock frequency of
27 MHz the PIXCLK frequency will be 13.5 MHz. The
pixel clock out can be shifted relative to the data out by
setting bit 8-11 of Reg0x07 appropriately.
Reset
Reg0x0D Reset
This register is used to reset the sensor to its default,
power-up state. To reset the MT9V011, first write a “1”
into bit 0 of this register, then write a “0” into bit 0 to
resume operation.
Table 8:
Vertical Blanking
REG0X06
# DARK ROWS
0
0
2
4
1-2
3+
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